Patents by Inventor Cem Basceri

Cem Basceri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD AND SYSTEM FOR BINDING HALIDE-BASED CONTAMINANTS
    Publication number: 20110147935
    Abstract: A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided.
    Type: Application
    Filed: March 4, 2011
    Publication date: June 23, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Garo J. Derderian, Cem Basceri, Donald L. Westmoreland
  • Methods of titanium deposition
    Patent number: 7947597
    Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: May 24, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Joel A. Drewes, Cem Basceri, Demetrius Sarigiannis
  • Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
    Patent number: 7923308
    Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 12, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Gurtej S. Sandhu, H. Montgomery Manning
  • Method and system for binding halide-based contaminants
    Patent number: 7922818
    Abstract: A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: April 12, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Cem Basceri, Donald L. Westmoreland
  • Methods for forming small-scale capacitor structures
    Patent number: 7906393
    Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 ?.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: March 15, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Lingyi A. Zheng, Trung T. Doan, Lyle D. Breiner, Er-Xuan Ping, Kevin L. Beaman, Ronald A. Weimer, Cem Basceri, David J. Kubista
  • Methods of forming vertical transistor structures
    Patent number: 7846798
    Abstract: The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: December 7, 2010
    Assignee: Micron Technology, Inc.
    Inventors: H. Montgomery Manning, Kunal R. Parekh, Cem Basceri, Gurtej S. Sandhu
  • METHODS AND SYSTEMS FOR CONTROLLING TEMPERATURE DURING MICROFEATURE WORKPIECE PROCESSING, E.G., CVD DEPOSITION
    Publication number: 20100282164
    Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
    Type: Application
    Filed: July 20, 2010
    Publication date: November 11, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kevin L. Beaman, Trung T. Doan, Lyle D. Breiner, Ronald A. Weimer, Er-Xuan Ping, David J. Kubista, Cem Basceri, Lingyi A. Zheng
  • Method of Forming a Layer Comprising Epitaxial Silicon, and a Field Effect Transistor
    Publication number: 20100258857
    Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
    Type: Application
    Filed: June 22, 2010
    Publication date: October 14, 2010
    Inventors: Nirmal Ramaswamy, Gurtej S. Sandhu, Cem Basceri, Eric R. Blomiley
  • Methods of depositing materials over substrates, and methods of forming layers over substrates
    Patent number: 7794787
    Abstract: The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is utilized to introduce at least one precursor into a chamber during ALD, and in particular aspects the supercritical fluid is utilized to introduce multiple precursors into the reaction chamber during ALD. The invention can be utilized to form any of various materials, including metal-containing materials, such as, for example, metal oxides, metal nitrides, and materials consisting of metal. Metal oxides can be formed by utilizing a supercritical fluid can be utilized to introduce a metal-containing precursor into reaction chamber, with the precursor then forming a metal-containing layer over a surface of a substrate. Subsequently, the metal-containing layer can be reacted with oxygen to convert at least some of the metal within the layer to metal oxide.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: September 14, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri
  • Methods and systems for controlling temperature during microfeature workpiece processing, E.G. CVD deposition
    Patent number: 7771537
    Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: August 10, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kevin L. Beaman, Trung T. Doan, Lyle D. Breiner, Ronald A. Weimer, Er-Xuan Ping, David J. Kubista, Cem Basceri, Lingyi A. Zheng
  • Methods of forming vertical transistor structures
    Patent number: 7767525
    Abstract: The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: August 3, 2010
    Assignee: Micron Technology, Inc.
    Inventors: H. Montgomery Manning, Kunal R. Parekh, Cem Basceri, Gurtej S. Sandhu
  • Integrated circuitry
    Patent number: 7768036
    Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: August 3, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Gurtej S. Sandhu, Cem Basceri, Eric R. Blomiley
  • Semiconductor device comprising a junction having a plurality of rings
    Patent number: 7768092
    Abstract: A semiconductor device comprises a first layer (1) of a wide band gap semiconductor material doped according to a first conductivity type and a second layer (3) on top thereof designed to form a junction blocking current in the reverse biased state of the device at the interface to said first layer. The device comprises extension means for extending a termination of the junction laterally with respect to the lateral border (6) of the second layer. This extension means comprises a plurality of rings (16-21) in juxtaposition laterally surrounding said junction (15) and being arranged as seen in the lateral direction away from said junction alternatively a ring (16-18) of a semiconductor material of a second conductivity type opposite to that of said first layer and a ring (19-21) of a semi-insulating material.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: August 3, 2010
    Assignee: Cree Sweden AB
    Inventors: Christopher Harris, Cem Basceri
  • Dielectric relaxation memory
    Patent number: 7751228
    Abstract: A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: July 6, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Gurtej Sandhu
  • Methods of Titanium Deposition
    Publication number: 20100167542
    Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.
    Type: Application
    Filed: March 9, 2010
    Publication date: July 1, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Joel A. Drewes, Cem Basceri, Demetrius Sarigiannis
  • Methods of forming capacitors
    Patent number: 7741175
    Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The capacitor dielectric region has an exposed oxide containing surface. The exposed oxide containing surface of the capacitor dielectric region is treated with at least one of a borane or a silane. A second capacitor electrode is deposited over the treated oxide containing surface. The second capacitor electrode has an inner metal surface contacting against the treated oxide containing surface. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: June 22, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Matthew W. Miller, Cem Basceri
  • Semiconductor device
    Patent number: 7728403
    Abstract: A semiconductor device of unipolar type has Schottky-contacts (6) laterally separated by regions in the form of additional layers (7, 7?) of semiconductor material on top of a drift layer (3). Said additional layers being doped according to a conductivity type being opposite to the one of the drift layer. At least one (7?) of the additional layers has a substantially larger lateral extension and thereby larger area of the interface to the drift layer than adjacent such layers (7) for facilitating the building-up of a sufficient voltage between that layer and the drift layer for injecting minority charge carriers into the drift layer upon surge for surge protection.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: June 1, 2010
    Assignee: Cree Sweden AB
    Inventors: Christopher Harris, Cem Basceri, Kent Bertilsson
  • Reactors, systems and methods for depositing thin films onto microfeature workpieces
    Patent number: 7699932
    Abstract: A reactor, system including reactors, and methods for depositing thin films on microfeature workpieces comprising a reaction vessel having a chamber, a gas distributor attached to the reaction vessel, a workpiece holder in the chamber, and a side unit in the reaction vessel at a location relative to the gas distributor and/or the workpiece holder. The gas distributor has a plurality of primary outlets open to the chamber, and the workpiece holder has a process site aligned with the primary outlets. The side unit has a secondary outlet open to the chamber that operates independently of the primary outlets. One of the inner compartment, the side unit and/or the workpiece holder can be movable between a first position to form a small-volume cell for introducing the reactant gases to the microfeature workpiece and a second position to form a large volume space for purging the reactant gases.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: April 20, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Matthew W. Miller, Cem Basceri
  • Methods of titanium deposition
    Patent number: 7700480
    Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: April 20, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Joel A. Drewes, Cem Basceri, Demetrius Sarigiannis
  • ONE-TRANSISTOR COMPOSITE-GATE MEMORY
    Publication number: 20100091574
    Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.
    Type: Application
    Filed: December 15, 2009
    Publication date: April 15, 2010
    Inventors: Cem Basceri, Gurtej S. Sandhu