Abstract: The image sensor has improvements for suppressing cross talk without degrading red light response. This is accomplished by implanting a deep p+ layer 42 under blue and green pixels 24 and 22 but not under red pixels 20 in a standard RGB pattern color filter array.

Abstract: The image sensor has improvements for suppressing cross talk without degrading red light response. This is accomplished by implanting a deep p+ layer 42 under blue and green pixels 24 and 22 but not under red pixels 20 in a standard RGB pattern color filter array.

Abstract: An interpoly dielectric is formed using only a single layer of oxide and a single layer of nitride to allow a reduction in thickness. The nitride is thermally grown on silicon in a nitrogen environment to maintain a high quality layer, while the oxide is deposited by LPCVD.

Abstract: A method for use in erasing data stored in a memory cell includes asserting a voltage differential across a tank region and a gate region of the memory cell, wherein the tank region has a first conductivity type and the tank region is located within a well region of a second conductivity type. The method also includes floating the voltage level of a source region and a drain region of the memory cell, wherein the source region and the drain region are located within the tank region and have the second conductivity type. The method additionally includes discharging a charge stored in the drain region by electrically connecting the source region to an electric potential lower than the potential of the drain region and electrically connecting the well region and the tank region to a potential lower than their existing potentials.

Abstract: A forward biased diode 40 is used to charge up a photodiode 26 rather than an NMOS transistor. This photodiode charging mechanism increases the dynamic range and optical response of active pixel arrays, and improves the scalability of the pixel element.

Abstract: A method for use in erasing data stored in a memory cell includes asserting a voltage differential across a tank region and a gate region of the memory cell, wherein the tank region has a first conductivity type and the tank region is located within a well region of a second conductivity type. The method also includes floating the voltage level of a source region and a drain region of the memory cell, wherein the source region and the drain region are located within the tank region and have the second conductivity type. The method additionally includes discharging a charge stored in the drain region by electrically connecting the source region to an electric potential lower than the potential of the drain region and electrically connecting the well region and the tank region to a potential lower than their existing potentials.

Abstract: An interpoly dielectric is formed using only a single layer of oxide and a single layer of nitride to allow a reduction in thickness. The nitride is thermally grown on silicon in a nitrogen environment to maintain a high quality layer, while the oxide is deposited by LPCVD.

Abstract: A semiconductor device includes a substrate and an oxide layer disposed outwardly from the substrate. The semiconductor device also includes a polysilicon layer disposed outwardly from the oxide layer, the oxide layer having an interface between the oxide layer and the polysilicon layer, the interface having asperities such that the barrier potential between the polysilicon layer and the substrate is reduced in response to the asperities.

Abstract: A transistor 10 is formed on an outer surface of a substrate 12. The transistor comprises a floating gate 18 and a control gate 20. An outer encapsulation layer 22 and sidewall bodies 26 and 28 comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewall bodies 26 and 28 and the layer 22 can be used as an etch stop during the formation of a drain contact 38. These layers will also permit the transmission of ultraviolet radiation to the floating gate 18 to enable the erasure of floating gate 18.

Abstract: A transistor 10 is formed on an outer surface of a substrate 12. The transistor comprises a floating gate 18 and a control gate 20. An outer encapsulation layer 22 and sidewalk bodies 26 and 28 comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewalk bodies 26 and 28 and the layer 22 can be used as an etch stop during the formation of a drain contact 38. These layers will also permit the transmission of ultraviolet radiation to the floating gate 18 to enable the erasure of floating gate 18.

Abstract: The invention comprises an integrated circuit including integral high and low-voltage peripheral transistors and a method for making the integrated circuit. In one aspect of the invention, a method of integrating high and low voltage transistors into a floating gate memory array comprises the steps of forming a tunnel oxide layer outwardly from a semiconductor substrate, forming a floating gate layer disposed outwardly from the tunnel oxide layer and forming an insulator layer disposed outwardly from the floating gate layer to create a first intermediate structure. The method further includes the steps of masking a first region and a second region of the first intermediate structure leaving a third region unmasked, removing at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer from the third region and forming a first dielectric layer disposed outwardly from the substrate in a region approximately coextensive with the third region.

Abstract: A transistor 10 is formed on an outer surface of a substrate 12. The transistor comprises a floating gate 18 and a control gate 20. An outer encapsulation layer 22 and sidewall bodies 26 and 28 comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewall bodies 26 and 28 and the layer 22 can be used as an etch stop during the formation of a drain contact 38. These layers will also permit the transmission of ultraviolet radiation to the floating gate 18 to enable the erasure of floating gate 18.

Abstract: The invention comprises a method of forming an integrated circuit, the method comprising: (1) forming a first dielectric layer disposed outwardly from a semiconductor substrate; (2) forming a first intermediate structure outwardly from the a dielectric layer, the first intermediate structure comprising a floating gate layer disposed outwardly from the first dielectric layer, a second dielectric layer disposed outwardly from the floating gate layer, and a first polysilicon layer disposed outwardly from the second dielectric layer; (3) removing regions of the first intermediate structure to form at least one gate stack disposed outwardly from the first dielectric layer; and (4) forming at least one dielectric isolation region after the formation of the gate stacks, wherein the at least one dielectric isolation region is disposed between two gate stacks.

Abstract: A CHE programmed memory device (30) avoids forward biasing at an isolated P-well (38) junction with a deep N-well (36) and prevents emitting electrons that may cause voltage buildup across the isolated P-well region (38) by applying a forward bias current (50) or voltage source (40) connected to the deep N-well region (36) for slightly forward biasing the deep N-well region. This maintains the voltage drop of isolated P-well region (38) below the diode turn-on voltage.

Abstract: A method of forming a floating gate memory array is provided that uses a two step etch process to prevent the formation of unwanted trenches 66 into the semiconductor substrate 26. The process may be accomplished by a first etch which is substantially not selective between silicon and dielectric materials. A second etch process is then used which is highly selective to dielectric materials.

Abstract: A method of fabricating a semiconductor device having a memory array (9) that includes a source line (24) is provided. The method of forming the source line (24) may include providing a semiconductor substrate (52) having a source region (60) separated from a drain region (62) by a channel region (64). An isolation structure (70) may be formed in the semiconductor substrate (52). The isolation structure (70) may cross the source region (60), the drain region (62), and the channel region (64) of the semiconductor substrate (52). An isolation dielectric material (78) may be formed within the isolation structure (70). A continuous stack structure (50) may be formed outwardly from the channel region (64) of the semiconductor substrate (52) and the isolation structure (70). A first photomask (100) may be formed outwardly from the continuous stack structure (50) and the semiconductor substrate (52).

Abstract: This invention provides a cost-effective, easy-to-integrate Flash EPROM cell array. Starting with a substrate (31) of first conductivity-type, a first diffusion (30) of second conductivity-type forms the sources (11), and the connections between sources, of all of the memory cells (10) of the array. A second diffusion (32) of first conductivity-type forms the channel of at least one memory cell (10) in the array. A floating gate (13) and a control gate (14) of that memory cell (10) are located over, and insulated from, a junction of the first diffusion and the second diffusion. A third diffusion (33) of second conductivity-type is isolated in the second diffusion (32) to form the drain (12) of the memory cell (10). During operation, only positive voltages may be used for programming and erasing of the cells (10), thus eliminating the need for negative voltages and for triple-well diffusions. The cell array of this invention requires little or no current for Fowler-Nordheim erase operation.

Abstract: A FLASH EPROM layout with straight gate and isolation structures to improve scalability and eliminate the need for self-aligned source process.

Abstract: A CHE programmed memory device (30) avoids forward biasing at an isolated P-well (38) junction with a deep N-well (36) and prevents emitting electrons that may cause voltage buildup across the isolated P-well region (38) by applying a forward bias current (50) or voltage source (40) connected to the deep N-well region (36) for slightly forward biasing the deep N-well region. This maintains the voltage drop of isolated P-well region (38) below the diode turn-on voltage.

Abstract: A system for testing and adjusting threshold voltages in flash EEPROMs is disclosed. The system includes a memory cell array (5) comprising a plurality of cell columns. Each cell column includes a plurality of memory cells (10). Each memory cell (10) has a control gate terminal (14), a drain terminal (12) and a source terminal 11. A control system comprising a wordline decoder (16), a column decoder (19) and a microprocessor (21) applies selected voltages to the respective terminals of the memory cells (10), and selects one of the plurality of cell columns for compaction verification. A detector (30) determines whether any one of the memory cells (10) of the selected cell column has a threshold voltage below a predetermined positive voltage, and supplies an output signal to the control system. The control system increases respective threshold voltages of the memory cells (10) of the selected cell column in response to the output signal of the detector (30).