Abstract: A selector includes a carbon material that includes carbon and a trivalent element that is chemically bond to cardon; and a dopant material implanted to the carbon material to form trap sites of conductive carriers based on a chemical bond between the carbon and the trivalent element in the carbon. A method for fabricating a selector includes forming a carbon layer that includes carbon; chemically reacting a trivalent element with the carbon in the carbon layer; and implanting a dopant through an ion implantation process.

Abstract: A selector includes a base material including carbon; and a dopant implanted into the base material. A method for fabricating a selector includes forming a carbon layer and implanting a dopant into the carbon layer. A semiconductor device includes a selector pattern including carbon as a base material and a dopant implanted through an ion implantation process; and a memory pattern disposed in an upper portion or a lower portion of the selector pattern.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: a selector pattern configured to exhibit different electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage; an interlayer insulating layer surrounding a sidewall of the selector pattern and having an opening disposed over the selector pattern; and an electrode disposed in the opening and having a width that is maximum at an uppermost portion of the opening, and wherein the uppermost portion of the opening has a rounded edge in a cross-sectional view.

Abstract: Semiconductor devices and methods for fabricating semiconductor memory devices are disclosed. In an embodiment, a semiconductor device includes: a selector pattern configured to exhibit a threshold switching behavior; an insulating layer structured to a sidewall of the selector pattern and include an opening disposed within the insulating layer over the selector pattern; and an electrode formed in the opening to a thickness that blocks an entrance of the opening and does not completely fill the opening.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a selector pattern including an insulating material doped with a dopant to exhibit different electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage, wherein the selector pattern includes a first region that is formed in an edge extending from a sidewall of the selector pattern and a second region that has a sidewall in contact with the first region, and a concentration of the dopant in the first region is different from a concentration of the dopant in the second region.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: a substrate; a pattern disposed over the substrate; a hard mask pattern that is conductive and disposed over the pattern, the hard mask pattern including a lower hard mask pattern and an upper hard mask pattern over the lower hard mask pattern; a conductive pattern disposed over the hard mask pattern and electrically connected to the pattern through the hard mask pattern; and an insulating layer covering a sidewall of the pattern and a sidewall of the lower hard mask pattern, wherein the upper hard mask pattern is disposed to protrude from the insulating layer.

Abstract: A semiconductor device includes a plurality of memory cells. Each memory cell includes: a first electrode layer; a second electrode layer; a memory layer electrically connected to the second electrode layer and configured to store data; a selector layer interposed between the first electrode layer and the second electrode layer and configured to control an access to the memory layer, the selector layer including an insulating material layer doped with a dopant, wherein at least one of the first electrode layer and the second electrode layer includes a first sub-electrode layer, and a second sub-electrode layer interposed between the first sub-electrode layer and the selector layer and including a material having a work function greater than a work function of the first sub-electrode layer.

Abstract: A semiconductor device includes a plurality of memory cells. Each memory cell includes: a memory layer configured to store data; and a selector layer configured to control an access to the memory layer, wherein the selector layer includes a layer which includes an insulating material and a porous material that are mixed, and a dopant that is present in the layer and breaks a bond between constituent elements of the insulating material.

Abstract: Semiconductor devices and methods for fabricating semiconductor devices are disclosed. In some implementations, a semiconductor device may include a first electrode layer; a second electrode layer disposed over the first electrode layer and spaced apart from the first electrode layer; and a selector layer disposed between the first electrode layer and the second electrode layer and including an insulating material that contains at least a dopant and carbon, wherein a carbon concentration at a first portion of the selector layer adjacent to the second electrode layer is higher than a carbon concentration at a second portion of the selector layer adjacent to the first electrode layer.

Abstract: A method for fabricating an electrode may include: forming a carbon layer; performing an ion beam etch process to planarize and harden a surface of the carbon layer on the carbon layer; and performing an impurity doping process to dope an impurity into the carbon layer.

Abstract: A method for fabricating a selector may include: forming an insulating layer; doping the insulating layer with dopants by performing an ion implantation process; and performing a subsequent process to the insulating layer doped with the dopants for restoring damage caused by the ion implantation process.

Abstract: A semiconductor device may include a first pattern including any one of a selector layer or a variable resistance layer and a middle electrode layer disposed over any one of the selector layer or the variable resistance layer; and a second pattern disposed over the first pattern and including the other one of the selector layer or the variable resistance layer, wherein a width of the second pattern may be the same as or greater than a width of the first pattern.

Abstract: According to one embodiment, a magnetic: memory device includes a stacked structure in which a magnetoresistance effect element and a switching element are stacked. The switching element is provided on a lower layer side of the magnetoresistance effect element, and when viewed in a stacking direction of the magnetoresistance effect element and the switching element, a pattern of the switching element is located inside a pattern of the magnetoresistance effect element.

Abstract: A semiconductor device may include: a memory cell disposed over a substrate and including a variable resistance layer and a selector layer; a protection layer disposed on side surfaces of the memory cell and an upper surface of the substrate on which the memory cell is not disposed; and a first encapsulation layer disposed on the memory cell and the protection layer, wherein the protection layer may include a treated surface that is modified by a material including helium.

Abstract: A method for fabricating a semiconductor device including a plurality of memory cells. The method includes: forming a first electrode layer; forming an initial Si-containing layer over the first electrode layer; performing a radical oxidation process to covert a first portion of the initial Si-containing layer into an oxide layer including silicon dioxide (SiO2) and form a Si-containing layer under the oxide layer by using a second portion of the initial Si-containing layer; and incorporating a dopant into the oxide layer by an ion implantation process to form a selector pattern.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.