Abstract: According to one embodiment, a magnetic: memory device includes a stacked structure in which a magnetoresistance effect element and a switching element are stacked. The switching element is provided on a lower layer side of the magnetoresistance effect element, and when viewed in a stacking direction of the magnetoresistance effect element and the switching element, a pattern of the switching element is located inside a pattern of the magnetoresistance effect element.

Abstract: A semiconductor device may include: a memory cell disposed over a substrate and including a variable resistance layer and a selector layer; a protection layer disposed on side surfaces of the memory cell and an upper surface of the substrate on which the memory cell is not disposed; and a first encapsulation layer disposed on the memory cell and the protection layer, wherein the protection layer may include a treated surface that is modified by a material including helium.

Abstract: A method for fabricating a semiconductor device including a plurality of memory cells. The method includes: forming a first electrode layer; forming an initial Si-containing layer over the first electrode layer; performing a radical oxidation process to covert a first portion of the initial Si-containing layer into an oxide layer including silicon dioxide (SiO2) and form a Si-containing layer under the oxide layer by using a second portion of the initial Si-containing layer; and incorporating a dopant into the oxide layer by an ion implantation process to form a selector pattern.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.

Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Abstract: An electronic device that includes a first structure including a first magnetic layer, a second magnetic layer, and a tunnel barrier layer which is interposed between the first magnetic layer and the second magnetic layer; and a second structure disposed over the first structure, and including a magnetic correction layer for correcting a magnetic field of the first structure, wherein a width of a bottom surface of the second structure is larger than a width of a top surface of the first structure.

Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.

Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer; and a protection layer including a pillar-shaped magnetic compensation layer and a non-magnetic layer, which are formed on the sidewall of the variable resistance element.

Abstract: Electronic devices have a semiconductor memory unit including a magnetization compensation layer in a contact plug. One implementation of the semiconductor memory unit includes a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer, and a contact plug arranged in at least one side of the variable resistance element and comprising a magnetization compensation layer. Another implementation includes a variable resistance element having a stacked structure of a first magnetic layer having a variable magnetization, a tunnel barrier layer, and a second magnetic layer having a pinned magnetization; and a contact plug arranged at one side of and separated from the variable resistance element to include a magnetization compensation layer that produces a magnetic field to reduce an influence of a magnetic field of the second magnetic layer on the first magnetic layer.

Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.

Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: Electronic devices have a semiconductor memory unit including a magnetization compensation layer in a contact plug. One implementation of the semiconductor memory unit includes a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer, and a contact plug arranged in at least one side of the variable resistance element and comprising a magnetization compensation layer. Another implementation includes a variable resistance element having a stacked structure of a first magnetic layer having a variable magnetization, a tunnel barrier layer, and a second magnetic layer having a pinned magnetization; and a contact plug arranged at one side of and separated from the variable resistance element to include a magnetization compensation layer that produces a magnetic field to reduce an influence of a magnetic field of the second magnetic layer on the first magnetic layer.

Abstract: The disclosed technology provides an electronic device and a fabrication method thereof, in which an etching margin in formation of a variable resistance element is secured and process difficulty is reduced. An electronic device according to an implementation includes a semiconductor memory, the semiconductor memory including: a variable resistance element including a stack of a first magnetic layer, a tunnel barrier layer and a second magnetic layer; a contact plug coupling a top of the variable resistance element and including a magnetism correcting layer; and a conductive line coupled to the variable resistance element through the contact plug including the magnetism correcting layer.

Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a seed layer including conductive hafnium silicate; a first magnetic layer formed over the seed layer; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer.