Patents by Inventor Chad A. Cobbley
Chad A. Cobbley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7387902Abstract: The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the chip with a transparent lid. In another embodiment of the invention, the perimeter area of a chip, including interconnections such as wire bonds and bond pads, is encapsulated with a liquid dispensed epoxy, and a transparent lid is attached. In yet another embodiment of the invention, chip encapsulation is accomplished with a unitary shell of entirely transparent material. In yet another embodiment of the invention, a substrate-mounted chip and a transparent lid are loaded into a transfer mold that holds them in optimal alignment. The transfer mold is then filled with molding compound.Type: GrantFiled: October 15, 2005Date of Patent: June 17, 2008Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Chad A. Cobbley
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Publication number: 20080093019Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: ApplicationFiled: December 19, 2007Publication date: April 24, 2008Applicant: MICRON TECHNOLOGY, INC.Inventors: Chad Cobbley, Steve Heppler
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Patent number: 7332376Abstract: Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the invention, a packaged microelectronic device assembly includes a microelectronic die, a substrate attached to the die, a protective casing covering a portion of the substrate, and a barrier projecting away from the surface of the substrate. The microelectronic die can have an integrated circuit and a plurality of bond-pads operatively coupled to the integrated circuit. The substrate can have a cap-zone defined by an area that is to be covered by the protective casing, a plurality of contact elements arranged in the cap-zone, a plurality of ball-pads arranged in a ball-pad array outside of the cap-zone, and a plurality of conductive lines coupling the contact elements to the ball-pads. The contact elements are electrically coupled to corresponding bond-pads on the microelectronic die, and the protective casing covers the cap-zone.Type: GrantFiled: September 5, 2006Date of Patent: February 19, 2008Assignee: Micron Technology, Inc.Inventor: Chad A. Cobbley
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Patent number: 7326316Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at feast one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: GrantFiled: June 22, 2004Date of Patent: February 5, 2008Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, Steve W. Heppler
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Patent number: 7288431Abstract: A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate by a molding technique such as transfer molding, injection molding, and spray molding, or using an encapsulating material. One or more dies, chips, or other semiconductor or microelectronic devices can be disposed on the substrate to form a die assembly. The stiffener can be molded to a substrate comprising one or more dies, over which an encapsulating material can be applied to produce a semiconductor die package.Type: GrantFiled: November 16, 2005Date of Patent: October 30, 2007Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, Cary J. Baerlocher
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Patent number: 7275676Abstract: Apparatus for placing conductive spheres on prefluxed bond pads of a substrate using a stencil plate with a pattern of through-holes positioned over the bond pads. Conductive spheres are placed in the through-holes by a moving feed mechanism and the spheres drop through the through-holes onto the bond pads. In one embodiment, the feed mechanism is a sphere hopper which crosses the entire through-hole pattern. In another embodiment, a shuttle plate fed spheres from a reservoir and reversibly moves about one-half of the pitch, moving from a non-discharge position to a discharge position.Type: GrantFiled: October 29, 2004Date of Patent: October 2, 2007Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, Michael B. Ball, Marjorie L. Waddel
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Patent number: 7239029Abstract: A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.Type: GrantFiled: January 9, 2003Date of Patent: July 3, 2007Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Cary J. Baerlocher, David J. Corisis, Chad A. Cobbley
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Publication number: 20070145556Abstract: Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dices coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package.Type: ApplicationFiled: February 20, 2007Publication date: June 28, 2007Inventors: Todd Bolken, Chad Cobbley
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Patent number: 7227252Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.Type: GrantFiled: August 17, 2005Date of Patent: June 5, 2007Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Chad A. Cobbley
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Publication number: 20070108579Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.Type: ApplicationFiled: December 28, 2006Publication date: May 17, 2007Inventors: Todd Bolken, Chad Cobbley
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Patent number: 7217596Abstract: A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.Type: GrantFiled: February 3, 2004Date of Patent: May 15, 2007Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, Timothy L. Jackson
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Patent number: 7195940Abstract: The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the chip with a transparent lid. In another embodiment of the invention, the perimeter area of a chip, including interconnections such as wire bonds and bond pads, is encapsulated with a liquid dispensed epoxy, and a transparent lid is attached. In yet another embodiment of the invention, chip encapsulation is accomplished with a unitary shell of entirely transparent material. In yet another embodiment of the invention, a substrate-mounted chip and a transparent lid are loaded into a transfer mold that holds them in optimal alignment. The transfer mold is then filled with molding compound to encapsulate the chip and interconnections, and to retain the transparent lid.Type: GrantFiled: February 21, 2003Date of Patent: March 27, 2007Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Chad A. Cobbley
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Publication number: 20070063335Abstract: Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the invention, a packaged microelectronic device assembly includes a microelectronic die, a substrate attached to the die, a protective casing covering a portion of the substrate, and a barrier projecting away from the surface of the substrate. The microelectronic die can have an integrated circuit and a plurality of bond-pads operatively coupled to the integrated circuit. The substrate can have a cap-zone defined by an area that is to be covered by the protective casing, a plurality of contact elements arranged in the cap-zone, a plurality of ball-pads arranged in a ball-pad array outside of the cap-zone, and a plurality of conductive lines coupling the contact elements to the ball-pads. The contact elements are electrically coupled to corresponding bond-pads on the microelectronic die, and the protective casing covers the cap-zone.Type: ApplicationFiled: September 5, 2006Publication date: March 22, 2007Applicant: Micron Technology, Inc.Inventor: Chad Cobbley
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Patent number: 7186576Abstract: Embodiments of the present technique relate to forming die stacks. Specifically, embodiments of the present technique include a method of forming and testing semiconductor die comprising forming a die stack of at least two semiconductor die without attaching either of the at least two semiconductor die to a substrate. Further, present embodiments include testing the semiconductor die in the die stack after the die stack is formed and prior to attaching either of the at least two semiconductor die to the substrate.Type: GrantFiled: November 4, 2005Date of Patent: March 6, 2007Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, Timothy L. Jackson
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Patent number: 7179681Abstract: Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dices coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package.Type: GrantFiled: December 23, 2004Date of Patent: February 20, 2007Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Chad A. Cobbley
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Patent number: 7169645Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.Type: GrantFiled: April 29, 2005Date of Patent: January 30, 2007Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Chad A. Cobbley
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Publication number: 20060290011Abstract: A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate by a molding technique such as transfer molding, injection molding, and spray molding, or using an encapsulating material. One or more dies, chips, or other semiconductor or microelectronic devices can be disposed on the substrate to form a die assembly. The stiffener can be molded to a substrate comprising one or more dies, over which an encapsulating material can be applied to produce a semiconductor die package.Type: ApplicationFiled: August 31, 2006Publication date: December 28, 2006Applicant: Micro Technology Inc.Inventors: Chad Cobbley, Cary Baerlocher
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Patent number: 7144245Abstract: A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.Type: GrantFiled: December 9, 2003Date of Patent: December 5, 2006Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Cary J. Baerlocher, David J. Corisis, Chad A. Cobbley
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Publication number: 20060267169Abstract: The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the chip with a transparent lid. In another embodiment of the invention, the perimeter area of a chip, including interconnections such as wire bonds and bond pads, is encapsulated with a liquid dispensed epoxy, and a transparent lid is attached. In yet another embodiment of the invention, chip encapsulation is accomplished with a unitary shell of entirely transparent material. In yet another embodiment of the invention, a substrate-mounted chip and a transparent lid are loaded into a transfer mold that holds them in optimal alignment.Type: ApplicationFiled: July 5, 2006Publication date: November 30, 2006Inventors: Todd Bolken, Chad Cobbley
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Patent number: 7134390Abstract: A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second portion extending from a second side thereof to minimize the shear stress between the material extruded therethrough and the stencil. The stencil allows for material to be extruded through the top of the stencil to the surface of the substrate and not contact the wall of the second portion of the aperture of the stencil. Since the material only contacts a small area of the first portion of the aperture near the top of the stencil, the material remains on the substrate and not in the aperture of the stencil.Type: GrantFiled: June 26, 2003Date of Patent: November 14, 2006Assignee: Micron Technology, Inc.Inventors: Chad Cobbley, Ford B. Grigg