Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.

Abstract: The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the chip with a transparent lid. In another embodiment of the invention, the perimeter area of a chip, including interconnections such as wire bonds and bond pads, is encapsulated with a liquid dispensed epoxy, and a transparent lid is attached. In yet another embodiment of the invention, chip encapsulation is accomplished with a unitary shell of entirely transparent material. In yet another embodiment of the invention, a substrate-mounted chip and a transparent lid are loaded into a transfer mold that holds them in optimal alignment. The transfer mold is then filled with molding compound.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: A method of attaching solder balls to a BGA package using a ball pickup tool is disclosed. An array of solder balls is formed on a first substrate for interconnecting with conductive sites on another substrate. The ball pickup tool picks up balls with a vacuum suction from a fluidized ball reservoir and utilizes a puff of gas to release the solder ball(s) carried thereon to conductive sites of a substrate for bonding thereto. In another embodiment, the bond pads of a substrate are coated with a flux or adhesive and lowered into a fluidized ball reservoir for direct attachment of solder balls.

Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with backside conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.

Abstract: Microelectronic imagers comprising imaging units and optics units with optics supports having threadless interfaces and methods for packaging such microelectronic imagers are disclosed herein. In one embodiment, the imaging unit can include a microelectronic substrate and a microelectronic die on and/or in the substrate. A first referencing element having one or more inclined steps arranged about an axis is fixed to the imaging unit. The imager can further include an optics unit having an optic member. A second referencing element having one or more complementary inclined steps is fixed to the optics unit. The second referencing element is seated with the first referencing element and at least one of the referencing elements can be rotatably adjusted with respect to the other to position the optic member at a desired location relative to the image sensor.

Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.

Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: Packaged microelectronic devices, interconnecting units for packaged microelectronic devices, and methods and apparatuses for packaging microelectronic devices with pressure release elements. In one aspect of the invention, a packaged microelectronic device includes a microelectronic die, an interconnecting unit coupled to the die, and a protective casing over the die. The interconnecting unit can have a substrate with a first side and a second side to which the die is attached, a plurality of contact elements operatively coupled to corresponding bond-pads on the die, and a plurality of ball-pads on the first side of the substrate electrically coupled to the contact elements. The protective casing can have at least a first cover encapsulating the die on the first side of the substrate. The packaged microelectronic device can also include a pressure relief element through at least a portion of the first cover and/or the substrate.

Abstract: A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second portion extending from a second side thereof to minimize the shear stress between the material extruded therethrough and the stencil. The stencil allows for material to be extruded through the top of the stencil to the surface of the substrate and not contact the wall of the second portion of the aperture of the stencil. Since the material only contacts a small area of the first portion of the aperture near the top of the stencil, the material remains on the substrate and not in the aperture of the stencil.

Abstract: A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second portion extending from a second side thereof to minimize the shear stress between the material extruded therethrough and the stencil. The stencil allows for material to be extruded through the top of the stencil to the surface of the substrate and not contact the wall of the second portion of the aperture of the stencil. Since the material only contacts a small area of the first portion of the aperture near the top of the stencil, the material remains on the substrate and not in the aperture of the stencil.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection bumps on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of “known good dice” (KGD) rework procedures during repair is eliminated.

Abstract: Various embodiments for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding an image sensor chip, and a transparent cover. The housing structure may cover substantially all of the interposer chip surface. In another embodiment, the housing structure also covers substantially all of the interposer edge surfaces. The housing structure may also cover substantially all of the interposer attachment surface. An image sensor chip is electrically connected to the interposer with sealed wire bond connections or with sealed flip-chip connections. The housing structure may include runners that enable simultaneous sealing of the interior of the image sensor package and of the transparent cover.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: A method and apparatus for assembling and packaging semiconductor dice. The semiconductor dice or assemblies of stacked and electrically interconnected semiconductor dice are placed at mutually spaced locations with respect to a common plane and encapsulated in a dielectric material so that end portions of discrete conductive elements extending outwardly from each semiconductor die adjacent the common plane are exposed through an outer surface of the dielectric material. Redistribution lines are formed to extend from the exposed end portions of the discrete conductive elements to predetermined locations over the outer surface of the encapsulant which correspond with another interconnect outline, such as terminal pads of a printed circuit board, and conductive bumps formed at the predetermined locations.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: A method of attaching solder balls to a BGA package using a ball pickup tool is disclosed. An array of solder balls is formed on a first substrate for interconnecting with conductive sites on another substrate. The ball pickup tool picks up balls with a vacuum suction from a fluidized ball reservoir and utilizes a puff of gas to release the solder ball(s) carried thereon to conductive sites of a substrate for bonding thereto. In another embodiment, the bond pads of a substrate are coated with a flux or adhesive and lowered into a fluidized ball reservoir for direct attachment of solder balls.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.