Abstract: Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dices coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package.

Abstract: A stackable package to create a 3-dimensional memory array using ball grid array technology. Specifically, memory chips are coupled to a pre-formed packages which have alignment features to allow for the stacking of the ball grid arrays. The alignment features are used to align and orient each package with respect to an adjacent package, substrate or printed circuit board. The alignment features also support the weight of the adjacent package during solder ball reflow to maintain stack height and parallelism between packages. Each memory device is serially connected to the adjacent memory device through the vias and solder balls on each package.

Abstract: A stackable package to create a 3-dimensional memory array using ball grid array technology. Specifically, memory chips are coupled to a pre-formed packages which have alignment features to allow for the stacking of the ball grid arrays. The alignment features are used to align and orient each package with respect to an adjacent package, substrate or printed circuit board. The alignment features also support the weight of the adjacent package during solder ball reflow to maintain stack height and parallelism between packages. Each memory device is serially connected to the adjacent memory device through the vias and solder balls on each package.

Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.

Abstract: A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.

Abstract: A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.

Abstract: A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.

Abstract: A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.

Abstract: Apparatus and method for attaching, assembling, and/or mounting a substrate to any semiconductor device or a flip-chip type semiconductor device.

Abstract: A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection bumps on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of “known good dice” (KGD) rework procedures during repair is eliminated.

Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

Abstract: A thin-stacked ball grid array (BGA) package is created by coupling a semi-conducting die to each of the opposing faces of an interposer having bond pads and circuitry on both faces. Solder balls on either side of each die and/or the interposer provide interconnects for stacking packages and also provide interconnects for module mounting. Each die may be electrically coupled to the interposer using wire bonds, “flip-chip” techniques, or other techniques as appropriate. A redistribution layer may also be formed on the outer surface of a bumped die to create connections between the die circuitry, ball pads and/or wire bonding pads. Because the two die are coupled to each other on opposite faces of the interposer, each package is extremely space-efficient. Individual packages may be stacked together prior to encapsulation or molding to further improve the stability and manufacturability of the stacked package.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situi test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy, being cured by pressing the integrated circuit (IC) dice against interconnection bumps on the substrate for electrical connection, while, those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of “known good dice” (KGD) rework procedures during repair is. eliminated.

Abstract: A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.

Abstract: An adhesive composition and methods incorporating the adhesive composition in semiconductor applications are provided. The adhesive composition is an instant setting adhesive composition that does not require external energy input such as heat or radiation such for application of the adhesive composition on a surface. The instant setting composition possesses sufficient thixotropic characteristics such that applying the instant setting adhesive composition to a surface can be accomplished by a variety of application techniques and in a variety of patterns. Once applied to the surface, the instant setting adhesive composition sets to retain the discrete pattern as applied, in a relatively short period of time, typically from about 0.10 to about 120 seconds at an ambient temperature, typically from 20° C. to 30° C.

Abstract: An adhesive composition and methods incorporating the adhesive composition in semiconductor applications are provided. The adhesive composition is an instant setting adhesive composition that does not require external energy input such as heat or radiation such for application of the adhesive composition on a surface. The instant setting composition possesses sufficient thixotropic characteristics such that applying the instant setting adhesive composition to a surface can be accomplished by a variety of application techniques and in a variety of patterns. Once applied to the surface, the instant setting adhesive composition sets to retain the discrete pattern as applied, in a relatively short period of time, typically from about 0.10 to about 120 seconds at an ambient temperature, typically from 20° C. to 30° C.