Abstract: A pixel of an image sensor includes: a semiconductor material substrate; a photosensitive region formed in the substrate, the photosensitive region generating photo-induced electrical charge in response to illumination with light; a storage node formed in the substrate proximate to the photosensitive region, the storage node selectively receiving and storing photo-induced electrical charge generated by the photosensitive region; and a shield formed over the storage node which inhibits light from reaching the storage node, the shield including an extension which protrudes into the substrate and surrounds an outer periphery of the storage node.

Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming an initial barrier material layer and a conductive layer on an upper surface of the dielectric layer and in the hole; removing part of the initial barrier material layer and part of the conductive layer to form a barrier material layer and a via element in the hole respectively and expose the upper surface of the dielectric layer. An upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.

Abstract: A method of orthopedic treatment includes steps of: by using a computer aided design (CAD) tool based on profile data that is related to a to-be-treated part of a bone of a patient, obtaining a model of a preliminary instrument that substantially fits the to-be-treated part; by using the CAD tool, obtaining a model of a patient specific instrument (PSI) based on the model of the preliminary instrument; producing the PSI based on the model of the PSI, the PSI being adjustable; performing medical operation on the to-be-treated part, and then attaching the PSI to the to-be-treated part; after attaching the PSI to the to-be-treated part, adjusting the PSI such that the PSI is adapted to real conditions of the to-be-treated part.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A ring oscillator includes an oscillation module, a first delay module, and a second delay module. The oscillation module is disposed in a first delay loop and a second delay loop and includes a first number of latches connected in series. The oscillation module has two input ends and two output ends, and the two input ends are respectively connected to a first node and a second node. The first delay module is disposed in the first delay loop and has an input end connected to a first output end of the oscillation module and an output end connected to the first node. The second delay module is disposed in the second delay loop and has an input end connected to a second output end of the oscillation module and an output end connected to the second node.

Abstract: Embodiments are directed to a method of operating a plasma processing system by retrofitting one or more components thereof. The method includes removing a holder from a gas supply mechanism of the plasma processing system. The holder includes a gas injector that is configured to provide gas received from a gas source to a plasma chamber of the plasma processing system. The method further includes reducing a size of a guide pin of the holder, installing the holder including the guide pin having the reduced size in the gas supply mechanism, and rotating the gas injector to change a flow of gas through the gas injector.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a gate structure on a substrate. A doped region is within the substrate. One or more dielectric materials are within a recess formed by one or more surfaces of the substrate. The doped region is laterally between the gate structure and the recess. A doped epitaxial material is within the recess and between the one or more dielectric materials and the doped region. The doped epitaxial material is asymmetric about a vertical line that extends through a lateral center of the doped epitaxial material.

Abstract: A method is provided for forming a light-shielding layer to block irradiation of light onto a light-sensitive storage region. The light-sensitive storage region is formed in a semiconductor substrate to store electric charges. A storage gate feature is formed over the light-sensitive storage region, and includes a polysilicon gate electrode that is disposed over the light-sensitive storage region. A metal layer is formed over the storage gate feature. A silicidation process is performed to transform a part of the metal layer that is in contact with the polysilicon gate electrode into a silicide light-shielding layer. A thermal process is performed to induce lateral growth of the silicide light-shielding layer to make the silicide light-shielding layer extend to cover a lateral surface of the storage gate feature. A process temperature of the thermal process is higher than that of the silicidation process.

Abstract: A display device includes a display, at least one light emitting element and at least one reflector. The display has a display surface and a back surface opposite to each other, and the display surface faces a front of the display. The light emitting element is disposed on the back surface. The reflector is slidably connected to the back surface and has a reflecting surface. When the reflector slides to a first position, the reflecting surface is hidden. When the reflector slides to a second position, the reflecting surface is exposed, such that light emitted from the light emitting element is reflected toward the front of the display by the reflecting surface.

Abstract: A method is provided for light shielding a charge storage device of an image sensor pixel that includes a photosensitive device and the charge storage device and a dielectric layer covering the photosensitive device and the charge storage device. The method includes performing etching of the dielectric layer to define an undercut volume beneath the dielectric layer and an access opening through the dielectric layer to the undercut volume, and performing physical vapor deposition (PVD) of a light blocking material to both: fill the undercut volume with the light blocking material to form a light blocking layer covering the charge storage device, and fill the access opening with the light blocking material to form a light blocking plug. An image sensor pixel formed by such a process, and an image sensor comprising an array of image sensor pixels, are also disclosed.

Abstract: Embodiments provide a ring oscillator and test method. The ring oscillator includes a first logic gate, a second logic gate, and a switch circuit. The first logic gate is configured to receive a test signal. The second logic gate includes a first NAND gate and a first NOR gate connected in sequence. An output terminal of the second logic gate is connected to an input terminal of the first logic gate, and the second logic gate is configured to receive output of the first logic gate to form a loop. The switch circuit includes a first switch circuit and a second switch circuit. The first switch circuit may be configured to control on/off of a power supply terminal of the first NAND gate and a ground terminal of the first NOR gate. The second switch circuit is configured to control on/off of a ground terminal of the first NAND gate.

Abstract: Embodiments of this invention provide a voltage output test circuit, a voltage divider output circuit, and a memory. The voltage output test circuit includes: a first voltage divider unit, including a first terminal and a second terminal, where the first terminal of the first voltage divider unit is connected to a test power supply, and the second terminal of the first voltage divider unit is connected to an output terminal; a second voltage divider unit, including a first terminal and a second terminal, where the first terminal of the second voltage divider unit is connected to a ground, and the second terminal of the second voltage divider unit is electrically connected to the output terminal; and a third voltage divider unit, configured to adjust a resistance between the output terminal and the ground.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a photodetector region provided in a substrate. A dielectric material is disposed within a trench defined by one or more interior surfaces of the substrate. The trench has a depth that extends from an upper surface of the substrate to within the substrate. A doped silicon material is disposed within the trench and has a sidewall facing away from the doped silicon material. The sidewall contacts a sidewall of the dielectric material along an interface extending along the depth of the trench.

Abstract: A method is provided for light shielding a charge storage device of an image sensor pixel that includes a photosensitive device and the charge storage device and a dielectric layer covering the photosensitive device and the charge storage device. The method includes performing etching of the dielectric layer to define an undercut volume beneath the dielectric layer and an access opening through the dielectric layer to the undercut volume, and performing physical vapor deposition (PVD) of a light blocking material to both: fill the undercut volume with the light blocking material to form a light blocking layer covering the charge storage device, and fill the access opening with the light blocking material to form a light blocking plug. An image sensor pixel formed by such a process, and an image sensor comprising an array of image sensor pixels, are also disclosed.

Abstract: A ring oscillator includes: an oscillation module, disposed in the first delay loop and the second delay loop and including a first number of latches connected in series, where the oscillation module has two input ends and two output ends, and the two input ends are respectively connected to the first node and the second node; a first delay module, disposed in the first delay loop, having an input end connected to a first output end of the oscillation module and an output end connected to the first node, and including a second number of latches connected in series, where the second number is even; and a second delay module, disposed in the second delay loop, having an input end connected to a second output end of the oscillation module and an output end connected to the second node, and including the second number of latches connected in series.

Abstract: A MEMS device includes a first multi-layer structure, a second multi-layer structure over the first multi-layer structure, a first semiconductor layer between the first and second multilayer structures, a first air gap separating the first multi-layer structure and the first semiconductor layer, a second air gap separating the first semiconductor layer and the second multi-layer structure, a plurality of semiconductor pillars, and a plurality of second semiconductor pillars. The first semiconductor pillars are exposed to the first air gap, and coupled to the first semiconductor layer and the first multi-layer structure. The second semiconductor pillars are exposed to the second air gap, and coupled to the first semiconductor layer and the second multi-layer structure.

Abstract: Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.

Abstract: A frame assembly includes a carrier and a frame. The carrier includes a bottom wall, and inner and outer side walls. The bottom wall is formed with an opening. The inner side wall is located in the opening. The inner and outer side walls extend from the bottom wall along an upright direction. The inner and outer side walls respectively include first inner and outer engaging structures. The outer side wall is spaced from the inner side wall. The frame includes a frame body, and inner and outer lateral walls. The inner and outer lateral walls extend from the frame body and respectively include second inner and outer engaging structures. The outer lateral wall is spaced from the inner lateral wall. The first and second inner engaging structures are engaged with each other, and the first and second outer engaging structures are engaged with each other.

Abstract: A method for forming a MEMS device includes following operations. A first semiconductor layer is formed over a substrate. A plurality of first pillars are formed over the first layer. A second layer is formed over the first pillars and the first layer. A plurality of second pillars are formed over the second layer. A third layer is formed over the second pillars and the second layer.