Patents by Inventor Chan Chen

Chan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11552205
    Abstract: Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Chang, Chia-Chan Chen
  • Publication number: 20220367737
    Abstract: Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Chang, Chia-Chan Chen
  • Publication number: 20220367538
    Abstract: Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Yueh-Chuan LEE, Shih-Hsien HUANG, Chia-Chan CHEN, Pu-Fang CHEN
  • Publication number: 20220344397
    Abstract: A method is provided for light shielding a charge storage device of an image sensor pixel that includes a photosensitive device and the charge storage device and a dielectric layer covering the photosensitive device and the charge storage device. The method includes performing etching of the dielectric layer to define an undercut volume beneath the dielectric layer and an access opening through the dielectric layer to the undercut volume, and performing physical vapor deposition (PVD) of a light blocking material to both: fill the undercut volume with the light blocking material to form a light blocking layer covering the charge storage device, and fill the access opening with the light blocking material to form a light blocking plug. An image sensor pixel formed by such a process, and an image sensor comprising an array of image sensor pixels, are also disclosed.
    Type: Application
    Filed: July 22, 2021
    Publication date: October 27, 2022
    Inventors: Cheng-Yen Li, Chia-Chan Chen, Meng-Chin Lee
  • Publication number: 20220320169
    Abstract: A photo-sensing device includes a semiconductor substrate, a photosensitive device, a dielectric layer and a light pipe. The photosensitive device is in the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The light pipe is over the photosensitive device and embedded in the dielectric layer. The light pipe includes a curved and convex light-incident surface.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chia-Chan Chen
  • Patent number: 11451219
    Abstract: A delay circuit and a delay structure are provided. The circuit includes: a first delay unit configured to delay a rising edge and/or a falling edge of a pulse signal, where, an input terminal of the first delay unit receives the pulse signal, and an output terminal of the first delay unit outputs a first delay signal, and a second delay unit, configured to delay the first delay signal, where an input terminal of the second delay unit is connected to the output terminal of the first delay unit, and an output terminal of the second delay unit outputs a second delay signal.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: September 20, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Weibing Shang, Anping Qiu, Chan Chen, Kangling Ji
  • Publication number: 20220293665
    Abstract: A method includes at least the following steps. A material layer is formed over an image capture chip. A patterned mask layer is formed on the material layer, wherein a pattern density of the patterned mask layer varies from a central region of the patterned mask layer to a periphery region of the patterned mask layer. The material layer is polished by using the patterned mask layer as a mask to form a lens layer including a single lens portion on the image capture chip.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 15, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chia-Chan Chen
  • Publication number: 20220257725
    Abstract: Disclosed herein are compositions and methods for treating mitochondrial dysfunction. The methods can include compositions capable of increasing or overexpressing ATAD1. The methods include restoring mitochondrial respiration and ATP production. The present disclosure provides a mechanism for peroxin (peroxisomal biogenesis factors) accumulation on mitochondria that affects respiration and ATP generation.
    Type: Application
    Filed: July 10, 2020
    Publication date: August 18, 2022
    Inventors: Esther Nuebel, Jared Rutter, Yu-Chan Chen, Joshua Bonkowsky
  • Patent number: 11416665
    Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 16, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Chen Huang, Yun-Ru Wu, Hsin-Chang Lin, Shu-Yi Kao, Chih-Chan Chen, Chia-Jung Hsu, Li-Yi Lin
  • Patent number: 11419221
    Abstract: A method of forming a protective film on at least one electronic module is provided. The method includes the following steps. A protective material is disposed on at least one electronic module such that the protective material and the electronic modules are in contact with each other. The electronic modules and the protective material disposed on the electronic modules are disposed in a chamber, and a first ambient pressure is provided in the chamber. The protective material in the chamber is heated to a first temperature to soften the protective material disposed on the electronic modules. After the protective material is softened, a second ambient pressure greater than the first ambient pressure is provided in the chamber, wherein a gas in the chamber directly pressurizes the protective material such that the protective material conformally covers a top of the electronic modules.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: August 16, 2022
    Assignee: ELEADTK CO., LTD.
    Inventors: Ching-Nan Chang, Sheng-Yu Lin, Ming-Chan Chen
  • Patent number: 11398512
    Abstract: A photo-sensing device includes a semiconductor substrate, a photosensitive device, a dielectric layer and a light pipe. The photosensitive device is in the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The light pipe is over the photosensitive device and embedded in the dielectric layer. The light pipe includes a curved and convex light-incident surface.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chia-Chan Chen
  • Publication number: 20220211999
    Abstract: An artificial retinal prosthesis is disclosed, which comprises a plurality of pixel group units to output a spatiotemporal electrical stimulation for inducing color perception. Each of the pixel group units comprises a main pixel unit and at least one surrounding pixel unit. The main pixel unit and the surrounding pixel unit respectively outputs an electrical stimulation waveform according to a first stimulation cycle and a second stimulation cycle. Both of the first stimulation cycle and the second stimulation cycle have a first-half duration and a second-half duration. The first-half duration of the first stimulation cycle has inactive period greater than 20% and less than 80% and the rest of the first stimulation cycle is active period. The second-half duration of the first stimulation cycle is inactive period. The first-half duration of the second stimulation cycle is active period and the second-half duration of the second stimulation cycle is inactive period.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Inventors: Feng-Hsiung HSU, Yung-Chan CHEN, Long-Sheng FAN, Lee LIN
  • Publication number: 20220212011
    Abstract: An artificial prosthesis is disclosed, which comprises a pixel array, a correlated double sampling unit, an analog-to-digital converter, a digital core, and a digital-to-analog converter. The digital core is configured to perform a calculation of electrical stimulation waveform of each of the pixels by using a processing function of an ANN. As such, the neural stimulation levels for artificial vision can be optimized.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Inventors: Feng-Hsiung HSU, Yung-Chan CHEN, Long-Sheng FAN
  • Patent number: 11380729
    Abstract: A method includes at least the following steps. A material layer is formed over an image capture chip. A patterned mask layer is formed on the material layer, wherein a pattern density of the patterned mask layer varies from a central region of the patterned mask layer to a periphery region of the patterned mask layer. The material layer is polished by using the patterned mask layer as a mask to form a lens layer including a single lens portion on the image capture chip.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chia-Chan Chen
  • Publication number: 20220155640
    Abstract: A frame assembly includes a carrier and a frame. The carrier includes a bottom wall, and inner and outer side walls. The bottom wall is formed with an opening. The inner side wall is located in the opening. The inner and outer side walls extend from the bottom wall along an upright direction. The inner and outer side walls respectively include first inner and outer engaging structures. The outer side wall is spaced from the inner side wall. The frame includes a frame body, and inner and outer lateral walls. The inner and outer lateral walls extend from the frame body and respectively include second inner and outer engaging structures. The outer lateral wall is spaced from the inner lateral wall. The first and second inner engaging structures are engaged with each other, and the first and second outer engaging structures are engaged with each other.
    Type: Application
    Filed: December 9, 2021
    Publication date: May 19, 2022
    Inventors: Teng-Yi HUANG, Chih-Chan CHEN, Tsung-Chen TUNG, Che-Chia HSU, Chin-Cheng HSIEH, Yung-Chieh CHAO, Chih-Hung CHUNG
  • Publication number: 20220158006
    Abstract: Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Chang, Chia-Chan Chen
  • Patent number: 11312123
    Abstract: A vacuum lamination system includes a film supply assembly, a film collection assembly, a lower lamination body, an upper lamination body, an air extractor, a moving assembly and a cutting assembly. The lower lamination body includes a first casing base and a lower heating assembly vertically movable and disposed in the first casing base. The lower heating assembly carries and moves the substrate so that the substrate is substantially flush with a top surface of the first casing base or retracted into the first casing base. The upper lamination body is vertically movable and disposed above the lower lamination body and includes an upper casing and an upper heating assembly disposed on the upper casing. The air extractor is connected to the lower lamination body. The moving assembly changes a height of a portion of the film. The cutting assembly cuts a portion of the film laminated onto the substrate.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: April 26, 2022
    Assignee: ELEADTK CO., LTD.
    Inventors: Ching-Nan Chang, Sheng-Yu Lin, Ming-Chan Chen
  • Publication number: 20220094344
    Abstract: A delay circuit and a delay structure are provided. The circuit includes: a first delay unit configured to delay a rising edge and/or a falling edge of a pulse signal, where, an input terminal of the first delay unit receives the pulse signal, and an output terminal of the first delay unit outputs a first delay signal, and a second delay unit, configured to delay the first delay signal, where an input terminal of the second delay unit is connected to the output terminal of the first delay unit, and an output terminal of the second delay unit outputs a second delay signal.
    Type: Application
    Filed: August 18, 2021
    Publication date: March 24, 2022
    Inventors: Weibing Shang, Anping Qiu, Chan Chen, Kangling Ji
  • Publication number: 20220059582
    Abstract: Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.
    Type: Application
    Filed: August 20, 2020
    Publication date: February 24, 2022
    Inventors: Yueh-Chuan LEE, Shih-Hsien HUANG, Chia-Chan CHEN, Pu-Fang Chen
  • Patent number: 11206493
    Abstract: A micro electro mechanical system (MEMS) microphone includes a first membrane, a second membrane, a third membrane disposed between the first membrane and the second membrane, a first cavity disposed between the first membrane and the third membrane and surrounded by a first wall, a second cavity disposed between the second membrane and the third membrane and surrounded by a second wall, and one or more first supports disposed in the first cavity and connecting the first membrane and the third membrane.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: December 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen Hsiung Yang, Chun-Wen Cheng, Chia-Hua Chu, En-Chan Chen