Patents by Inventor Chan H. Yoo

Chan H. Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190067248
    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Inventors: Chan H. Yoo, Ashok Pachamuthu
  • Publication number: 20190067034
    Abstract: Semiconductor devices with redistribution structures that do not include pre-formed substrates and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die attached to a redistribution structure and electrically coupled to the redistribution structure via a plurality of wire bonds. The semiconductor device can also include one or more second semiconductor dies stacked on the first semiconductor die, wherein one or more of the first and second semiconductor dies are electrically coupled to the redistribution structure via a plurality of wire bonds. The semiconductor device can also include a molded material over the first and/or second semiconductor dies and a surface of the redistribution structure.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Inventors: Ashok Pachamuthu, Chan H. Yoo, John F. Kaeding
  • Publication number: 20190067145
    Abstract: A semiconductor device having a semiconductor die, a redistribution layer (RDL), and an encapsulant. The RDL layer can be formed on a first surface of the semiconductor die. The encapsulant can enclose a second surface and side surfaces of the semiconductor die. The encapsulant can enclose side portions of the RDL.
    Type: Application
    Filed: August 22, 2017
    Publication date: February 28, 2019
    Inventors: Hyunsuk Chun, Shams U. Arifeen, Chan H. Yoo, Tracy N. Tennant
  • Publication number: 20190067247
    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Inventors: Chan H. Yoo, Mark E. Tuttle
  • Publication number: 20190035755
    Abstract: Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes. The sacrificial material may be removed to expose posts of the electrically conductive material. A stack of semiconductor dice may be placed between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack. The posts and the stack of semiconductor dice may be at least laterally encapsulated in an encapsulant. Bond pads of the one of the semiconductor dice may be electrically connected to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.
    Type: Application
    Filed: July 26, 2017
    Publication date: January 31, 2019
    Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
  • Patent number: 10192843
    Abstract: Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes. The sacrificial material may be removed to expose posts of the electrically conductive material. A stack of semiconductor dice may be placed between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack. The posts and the stack of semiconductor dice may be at least laterally encapsulated in an encapsulant. Bond pads of the one of the semiconductor dice may be electrically connected to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
  • Patent number: 10103038
    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: October 16, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
  • Publication number: 20070275540
    Abstract: Backside via formation in one or more dice prior to the one or more dice being attached to an underlying substrate is described herein. The resulting backside vias having substantially no air voids or air voids occupying not greater than 8 percent of the total volume of the backside vias.
    Type: Application
    Filed: May 24, 2006
    Publication date: November 29, 2007
    Inventors: Dale A. Hackitt, Dingying Xu, Salvatore A. Ruggero, Chan H. Yoo
  • Patent number: 6973236
    Abstract: A tapered waveguide improves insertion loss occurring at the slab/waveguide interface of an optical array waveguide grating (AWG). The tapered waveguide has two segments. The first segment decreases from a first thickness, nearest the slab of the AWG to a second thickness moving away from the slab. The second segment has a substantially constant or uniform thickness equal to the second thickness of the first segment. The second segment may also have a swallowtail shape comprising a forked end having two sidewalls tapered back towards the first segment. Light that would otherwise be lost at the slab/waveguide interface is instead captured by the tapered waveguide which laterally channels the light back into the waveguides thus mitigating insertion loss.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: December 6, 2005
    Assignee: Intel Corporation
    Inventors: Daniel W. So, Chan H. Yoo
  • Publication number: 20040120674
    Abstract: A tapered waveguide improves insertion loss occurring at the slab/waveguide interface of an optical array waveguide grating (AWG). The tapered waveguide has two segments. The first segment decreases from a first thickness, nearest the slab of the AWG to a second thickness moving away from the slab. The second segment has a substantially constant or uniform thickness equal to the second thickness of the first segment. The second segment may also have a swallowtail shape comprising a forked end having two sidewalls tapered back towards the first segment. Light that would otherwise be lost at the slab/waveguide interface is instead captured by the tapered waveguide which laterally channels the light back into the waveguides thus mitigating insertion loss.
    Type: Application
    Filed: December 24, 2002
    Publication date: June 24, 2004
    Inventors: Daniel W. So, Chan H. Yoo
  • Patent number: 5574770
    Abstract: A method for controlling an overload of a main processor by assigning to the main processor of a distributed switching system with a hierarchy structure a function of informing associated lower-level processors of an occurrence of the overload, an increase in call suppression, a decrease in call suppression and a release of the overload upon controlling the overload, and assigning to the lower-level processors a function of automatically calculating the number of calls to be processed in response to a demand of the main processor, and controlling traffic affecting the main processor on the basis of the result of the calculation, so as to maintain a stable service condition for the overload control interval.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: November 12, 1996
    Assignees: Electronics and Telecommunications Research Institute, Korea Telecommunication Authority
    Inventors: Chan H. Yoo, Byung S. Lee, Young S. Kim
  • Patent number: 5513257
    Abstract: A method for controlling an overload in a hybrid full electronic switching system, capable of maintaining a stable service condition for an overload control interval and realizing a priority control depending on the type of call by sorting an overload occurring in the system into an overload associated with processors adapted to execute services in a centralized manner and an overload associated with processors adapted to execute same services in a distributed manner and thereby automatically calculating numbers of calls to be accepted respectively for control intervals for two kinds of overloads in different control manners. The method includes two different control procedures respectively applied to a case wherein a reduction in overload can be carried out in a processor involving the overload and a case wherein a reduction in overload can be carried out by limiting services to be executed in other processors.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: April 30, 1996
    Assignees: Electronics and Telecommunications Research Institute, ABD Korea Telecommunications Authority
    Inventors: Chan H. Yoo, Byung S. Lee, Young S. Kim
  • Patent number: 5513255
    Abstract: A method for controlling an overload of distributed processors of a full electronic switching system, capable of automatically calculating the number of calls to be accepted for a current interval by use of the number of calls accepted for a previous interval and the number of standby processes of a call processing program so that only the number of calls corresponding to the number of services calculated is acceptable, thereby maintaining a stable service condition for an overload control interval, and capable of realizing a priority control depending on the type of call.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: April 30, 1996
    Assignees: Electronics and Telecommunication Research Institute, Korea Telecommunications Authority
    Inventors: Chan H. Yoo, Byung S. Lee, Young S. Kim
  • Patent number: 5241579
    Abstract: A status management method of this invention comprises: a first step of receiving a status alteration information of speech path device, analyzing each alteration status, and altering a count for each status; a second step of calculating a service reference value of each signalling service device as based on the number of subscriber lines for normal service in case that a status alteration device is subscriber line, and reporting a fault segregating limitation value of each signalling service device in case that said service reference value is altered; and a third step of analyzing a service status of each signalling service device according to said service reference value, and ending the status management on outputting a software alarm according to an analysis result of said service status.
    Type: Grant
    Filed: February 10, 1992
    Date of Patent: August 31, 1993
    Assignee: Korea Telecommunication Authority Electronics and Telecommunications Research Institute
    Inventors: Dae S. Kim, Byung H. Yae, Chan H. Yoo, Hyoung J. Park