Abstract: The present invention provides a composition for preventing, improving or treating periodontal diseases comprising extract of mangosteen. The composition of the present invention has excellent anti-bacterial and anti-inflammatory effects against bacteria inducing periodontal diseases as comprising extract of mangosteen, or alpha-mangosteen or gamma-mangosteen derived from thereof, and thereby it can be widely used for medicines and foods for preventing, improving or treating periodontal diseases.

Abstract: A Multiple-Input and Multiple-Output (MIMO) antenna having a plurality of isolation adjustment portions is provided. The MIMO antenna includes a plurality of radiation elements and a plurality of isolation adjustment portions. The plurality of radiation elements is symmetrically formed on the surfaces of the left and right sides of a dielectric element having a predetermined shape, is spaced apart from each other by a predetermined distance, operates in multiple frequency bands, and includes feeding portions, respectively. The plurality of isolation adjustment portions is coupled to the plurality of radiation elements so that they have electromagnetic characteristics different from those of the plurality of radiation elements, thereby improving isolation in each of the frequency bands in which the plurality of radiation elements operate.

Abstract: A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

Abstract: A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

Abstract: A Multiple-Input Multiple-Output (MIMO) antenna having parasitic elements is provided. The MIMO antenna includes a plurality of antenna elements, a plurality of parasitic elements, and a bridge. The plurality of antenna elements is symmetrically disposed on one side surface of a board while maintaining a predetermined distance therebetween. The plurality of parasitic elements is disposed on the other side surface of the board in a one-to-one correspondence with the plurality of antenna elements. The bridge is formed of a metal pattern line, and is configured to connect the plurality of parasitic elements to each other.

Abstract: A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage.

Abstract: A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

Abstract: A nonvolatile memory device includes a plurality of memory cells connected to a wordline and arranged in a row direction, bitlines connected to the plurality of memory cells, respectively, and a bitline bias circuit configured to separately control bias voltages provided to the bitlines according to positions of the memory cells along the row direction.

Abstract: A read operation method of a memory device includes applying a first voltage to each of a first memory cell and a second memory cell during a first read operation, applying the first voltage to the first memory cell and a second voltage to the second memory cell during a second read operation, and applying the second voltage to the first memory cell and the first voltage to the second memory cell during a third read operation.

Abstract: A Multiple-Input and Multiple-Output (MIMO) antenna having a plurality of isolation adjustment portions is provided. The MIMO antenna includes a plurality of radiation elements and a plurality of isolation adjustment portions. The plurality of radiation elements is symmetrically formed on the surfaces of the left and right sides of a dielectric element having a predetermined shape, is spaced apart from each other by a predetermined distance, operates in multiple frequency bands, and includes feeding portions, respectively. The plurality of isolation adjustment portions is coupled to the plurality of radiation elements so that they have electromagnetic characteristics different from those of the plurality of radiation elements, thereby improving isolation in each of the frequency bands in which the plurality of radiation elements operate.

Abstract: A Multiple-Input Multiple-Output (MIMO) antenna having parasitic elements is provided. The MIMO antenna includes a plurality of antenna elements, a plurality of parasitic elements, and a bridge. The plurality of antenna elements is symmetrically disposed on one side surface of a board while maintaining a predetermined distance therebetween. The plurality of parasitic elements is disposed on the other side surface of the board in a one-to-one correspondence with the plurality of antenna elements. The bridge is formed of a metal pattern line, and is configured to connect the plurality of parasitic elements to each other.

Abstract: A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

Abstract: A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage.

Abstract: A NAND flash array includes a first selection transistor coupled to a first selection line, a second selection transistor coupled to a second selection line, memory cells operably coupled to word lines and connected to each other in series between the first and second selection transistors, and a strapping line electrically connected to the first selection line.

Abstract: A read operation method of a memory device includes applying a first voltage to each of a first memory cell and a second memory cell during a first read operation, applying the first voltage to the first memory cell and a second voltage to the second memory cell during a second read operation, and applying the second voltage to the first memory cell and the first voltage to the second memory cell during a third read operation.

Abstract: A nonvolatile memory device includes a plurality of memory cells connected to a wordline and arranged in a row direction, bitlines connected to the plurality of memory cells, respectively, and a bitline bias circuit configured to separately control bias voltages provided to the bitlines according to positions of the memory cells along the row direction.

Abstract: A semiconductor memory device having a mat structure. The semiconductor memory device may comprise a first mat having a plurality of first memory cells and a second mat having a plurality of second memory cells. The first and second mats are formed in a single well region. The first and second mats may share a first well of a first conductivity type, and the first well may be formed in a second well of a second conductivity type. The second well may be formed in a semiconductor substrate of the first conductivity type. As a result, the semiconductor memory device according to embodiments of the present invention provide for higher integration density.

Abstract: A flash memory device comprises first and second mat structures connected to respective first and second high voltage lines, and a switch circuit connected between the first and second high voltage lines. The switch circuit supplies a program voltage from the first high voltage line to the second high voltage line during a first program operation of the flash memory device, and then supplies a voltage from the second high voltage line to the first high voltage line during a second program operation.

Abstract: A NAND flash array includes a first selection transistor coupled to a first selection line, a second selection transistor coupled to a second selection line, memory cells operably coupled to word lines and connected to each other in series between the first and second selection transistors, and a strapping line electrically connected to the first selection line.

Abstract: A flash memory device comprises first and second mat structures connected to respective first and second high voltage lines, and a switch circuit connected between the first and second high voltage lines. The switch circuit supplies a program voltage from the first high voltage line to the second high voltage line during a first program operation of the flash memory device, and then supplies a voltage from the second high voltage line to the first high voltage line during a second program operation.