Abstract: A semiconductor memory device having a mat structure. The semiconductor memory device may comprise a first mat having a plurality of first memory cells and a second mat having a plurality of second memory cells. The first and second mats are formed in a single well region. The first and second mats may share a first well of a first conductivity type, and the first well may be formed in a second well of a second conductivity type. The second well may be formed in a semiconductor substrate of the first conductivity type. As a result, the semiconductor memory device according to embodiments of the present invention provide for higher integration density.

Abstract: A flash memory device comprises first and second mat structures connected to respective first and second high voltage lines, and a switch circuit connected between the first and second high voltage lines. The switch circuit supplies a program voltage from the first high voltage line to the second high voltage line during a first program operation of the flash memory device, and then supplies a voltage from the second high voltage line to the first high voltage line during a second program operation.

Abstract: A NAND flash array includes a first selection transistor coupled to a first selection line, a second selection transistor coupled to a second selection line, memory cells operably coupled to word lines and connected to each other in series between the first and second selection transistors, and a strapping line electrically connected to the first selection line.

Abstract: A flash memory device comprises first and second mat structures connected to respective first and second high voltage lines, and a switch circuit connected between the first and second high voltage lines. The switch circuit supplies a program voltage from the first high voltage line to the second high voltage line during a first program operation of the flash memory device, and then supplies a voltage from the second high voltage line to the first high voltage line during a second program operation.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of data storage regions having a plurality of memory cells and a plurality of dummy regions occupying space between the plurality of data storage regions, at least one peripheral logic arranged around the memory cell array, and a control logic for controlling operations of the peripheral logic, wherein a plurality of signal lines for connecting the peripheral logic and the control logic are arranged in the plurality of dummy regions.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of data storage regions having a plurality of memory cells and a plurality of dummy regions occupying space between the plurality of data storage regions, at least one peripheral logic arranged around the memory cell array, and a control logic for controlling operations of the peripheral logic, wherein a plurality of signal lines for connecting the peripheral logic and the control logic are arranged in the plurality of dummy regions.

Abstract: A refrigerator includes a main body, freezing and refrigerating compartments formed in the main body, an evaporator for generating cool air, and a cool air dispersing system for dispersing cool air in the refrigerating compartment. The cool air dispersing system has a horizontal cool air dispersing device rotatable about a vertical axis for dispersing the cool air in a horizontal direction, a motor for rotating the horizontal cool air dispersing device, and a vertical cool air dispersing device for dispersing the cool air in the vertical direction. A force converting device is provided for vertically moving the vertical cool air dispersing device using a rotational force of the horizontal cool air dispersing device.