Patents by Inventor Chan-Hong Chern

Chan-Hong Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160173095
    Abstract: A level shifting circuit includes an input circuit, a leakage divider circuit, a skew inverter circuit and a buffering circuit. The input circuit has an input terminal configured to receive an input voltage. The input circuit is configured to receive a first voltage and a second voltage. The leakage divider circuit is configured to receive a third voltage. The leakage divider circuit is connected to the input circuit. The skew inverter circuit is configured to receive the third voltage. The skew inverter circuit is connected to the leakage divider circuit and the input circuit. The buffering circuit has a terminal configured to output an output voltage. The buffering circuit is connected to an output terminal of the skew inverter circuit. The level shifting circuit is free of capacitors.
    Type: Application
    Filed: February 22, 2016
    Publication date: June 16, 2016
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN
  • Patent number: 9360876
    Abstract: A voltage supply unit including a regulator unit, a voltage divider and a first current mirror. The regulator unit is configured to receive a first voltage signal and a second voltage signal, and is configured to generate a third voltage signal. The voltage divider is connected between the first current mirror and the regulator unit, and controls the second voltage signal. The first current mirror is connected to the regulator unit, an input voltage supply and the voltage divider. The first current mirror is configured to generate a first current signal and a second current signal, the second current signal is mirrored from the first current signal, the first current signal is controlled by the third voltage signal and the second current signal controls an output voltage supply signal.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 7, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Publication number: 20160155488
    Abstract: A method of operating a first voltage regulator includes electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage, and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array. The first voltage regulator is coupled to a second voltage regulator and reverse biasing the bulk of the transistor reduces a contention current between the first voltage regulator and the second voltage regulator.
    Type: Application
    Filed: February 3, 2016
    Publication date: June 2, 2016
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tien Chun YANG, Chih-Chang LIN, Yuwen SWEI
  • Publication number: 20160149564
    Abstract: A delay line circuit includes a plurality of delay units configured to receive an input signal and to provide a first output signal. The plurality of delay units is configured to selectively invert or relay the input signal to produce the first output signal based on a first instruction received from a delay line controller. A phase interpolator unit includes an offset unit configured to selectively add a speed control unit in the phase interpolator unit based on a second instruction received from the delay line controller. The phase interpolator unit is further configured to receive the first output signal and provide a second output signal.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tsung -Ching (Jim) HUANG, Chih-Chang LIN, Tien-Chun YANG
  • Publication number: 20160116930
    Abstract: A current generator includes an amplifier having a first terminal configured to receive a first voltage, a tunable resistance circuit coupled to an output terminal of the amplifier through a first transistor, a calibration circuit coupled to the tunable resistance circuit, and a second transistor. The second transistor includes a gate terminal coupled to the output terminal of the amplifier and a drain terminal coupled to a load. The calibration circuit is configured to adjust a resistance setting of the tunable resistance circuit.
    Type: Application
    Filed: January 6, 2016
    Publication date: April 28, 2016
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Chih-Chang Lin
  • Publication number: 20160087817
    Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 24, 2016
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Yuwen SWEI, Chih-Chang LIN, Tsung-Ching HUANG
  • Publication number: 20160086949
    Abstract: The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.
    Type: Application
    Filed: December 4, 2015
    Publication date: March 24, 2016
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Julie Tran, Jacklyn Chang
  • Patent number: 9293992
    Abstract: A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tzu Ching Chang, Min-Shueh Yuan, Yuwen Swei, Chih-Chang Lin, Chiang Pu, Ming-Chieh Huang, Kuoyuan Hsu
  • Publication number: 20160079849
    Abstract: An initialization device for a charge pump includes a driving circuit and a bias voltage circuit. The driving circuit is between two power supply nodes. The driving circuit includes a first node configured to be coupled to an output electrode of a capacitor in the charge pump. The bias voltage circuit is coupled to the two power supply nodes. The bias voltage circuit includes a second node coupled to a control terminal of the driving circuit. In response to an applied initialization signal, the bias voltage circuit is configured to output a bias voltage to the second node. The bias voltage has at least two levels that correspond to levels of the applied initialization signal. In response to the bias voltage, the driving circuit is configured to output an output signal having at least two levels that correspond to the at least two levels of the bias voltage.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 17, 2016
    Inventors: Chan-Hong CHERN, Chih-Chang LIN, Tsung-Ching HUANG, Ming-Chieh HUANG
  • Publication number: 20160072502
    Abstract: A circuit includes a first power node, a second power node, an output node, a plurality of first transistors and a plurality of second transistors. The plurality of first transistors is serially coupled between the first power node and the output node. The plurality of second transistors is serially coupled between the second power node and the output node.
    Type: Application
    Filed: November 18, 2015
    Publication date: March 10, 2016
    Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Publication number: 20160072279
    Abstract: A method of increasing a current flowing through an inductor includes receiving an input signal with a driver stage, the driver stage including the inductor coupled in series with a loading between an output node of the driver stage and a power line. In response to a transition in the input signal from a first voltage state to a second voltage state, a first current flowing through the loading and the inductor is increased. During the transition in the input signal, the current flowing through the inductor is increased by increasing a second current in a circuitry though a node between the inductor and the loading.
    Type: Application
    Filed: November 17, 2015
    Publication date: March 10, 2016
    Inventors: Tao Wen CHUNG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN, Yuwen SWEI
  • Publication number: 20160065194
    Abstract: A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller.
    Type: Application
    Filed: November 12, 2015
    Publication date: March 3, 2016
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Fu-Lung HSUEH
  • Patent number: 9275994
    Abstract: An integrated circuit comprises a gate electrode of at least one active transistor. The integrated circuit also comprises a first dummy gate electrode on a first side of the gate electrode. The integrated circuit further comprises a second dummy gate electrode on a second side of the gate electrode, the second side being opposite the first side. The integrated circuit additionally comprises a diffusion ring surrounding the gate electrode, the first dummy gate electrode, and the second dummy gate electrode. The integrated circuit also comprises a diffusion area extending from a first edge of the diffusion ring to a second edge of the diffusion ring.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mei-Hui Huang, Chan-Hong Chern
  • Patent number: 9276537
    Abstract: A method of sharing inductors for inductive peaking of an amplifier includes calculating a single stage inductance of a single stage for inductive peaking in order to have a stable impulse response. The method further includes determining a number of stages for shared inductance for inductive peaking. The method further includes sharing at least two inductors having the shared inductance among the determined number of stages for inductive peaking.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
  • Patent number: 9275719
    Abstract: A voltage regulator includes an amplifier, an output stage coupled with the amplifier, at least one back-bias circuit, and an output end coupled with the output stage and with the amplifier. The output stage includes at least one transistor having a bulk and a drain. The at least one back-bias circuit is coupled with the bulk of the at least one transistor. The output end is configured to be coupled with a memory array and with an output end of another voltage regulator. The back-bias circuit is configured to reduce a contention current between the voltage regulator and the other voltage regulator during a standby mode.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tien Chun Yang, Chih-Chang Lin, Yuwen Swei
  • Patent number: 9270276
    Abstract: A level shifting apparatus includes a first capacitor, a first side of the first capacitor configured to receive a first voltage. The level shifting apparatus further includes an edge detector configured to receive the first voltage. The level shifting apparatus further includes an output inverter connected to a second side of the first capacitor, the output inverter configured to output an voltage-level shifted signal of the level shifting apparatus. The level shifting apparatus further includes a latch loop configured to receive feedback the output signal to an input of the output inverter, wherein the edge detector is configured to selectively interrupt feedback of the output signal to the input of the output inverter.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: February 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
  • Publication number: 20160043071
    Abstract: An integrated circuit includes transistor and resistor. The transistor includes a gate stack. The gate stack includes a first dielectric layer, a first conductive layer over the first dielectric layer, a second conductive layer over the first conductive layer, and a second dielectric layer over the second conductive layer. The transistor also includes source/drain (S/D) regions adjacent to the gate stack. The resistor adjacent to the transistor, and includes a third dielectric layer.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 11, 2016
    Inventors: Chan-Hong CHERN, Fu-Lung HSUEH
  • Publication number: 20160036442
    Abstract: A level shifting apparatus includes a first capacitor, a first side of the first capacitor configured to receive a first voltage. The level shifting apparatus further includes an edge detector configured to receive the first voltage. The level shifting apparatus further includes an output inverter connected to a second side of the first capacitor, the output inverter configured to output an voltage-level shifted signal of the level shifting apparatus. The level shifting apparatus further includes a latch loop configured to receive feedback the output signal to an input of the output inverter, wherein the edge detector is configured to selectively interrupt feedback of the output signal to the input of the output inverter.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 4, 2016
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN
  • Patent number: 9236799
    Abstract: A current generator includes an amplifier having a first terminal configured to receive an input voltage, at least one tunable resistor coupled to a second terminal of the amplifier, a resistor calibration circuit coupled to the at least one tunable resistor, and at least one transistor. A gate of the at least one transistor is coupled to an output of the amplifier, and a terminal of the at least one transistor is coupled to the at least one tunable resistor or a load. The resistor calibration circuit is configured to adjust a resistance setting of the at least one tunable resistor to control a current level of the current generator based on a power supply voltage or a current of a reference resistor.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Chih-Chang Lin
  • Patent number: 9214933
    Abstract: A circuit includes a first power node configured to carry a voltage K·VDD, a second power node configured to carry a zero reference level, an output node, K P-type transistors serially coupled between the first power node and the output node, and K N-type transistors serially coupled between the second power node and the output node. Gates of the K P-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of source-gate voltages or absolute values of drain-gate voltages are equal to or less than VDD. Gates of the K N-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of gate-source voltages or gate-drain voltages are equal to or less than VDD.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 15, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh