Abstract: The present invention relates to a novel benzotriazole derivative compound, a tautomer thereof, a pharmaceutically acceptable salt thereof, a hydrate thereof, or a stereoisomer thereof, which are related to a compound for inhibiting ENPP1, a composition for inhibiting ENPP1, and a method for inhibiting ENPP1.

Abstract: A method of manufacturing a printed circuit board a includes preparing an insulating substrate on which a first metal layer is formed, stacking a resist laminate having a plurality of layers on the first metal layer, forming an opening exposing a portion of the first metal layer by patterning the stacked resist laminate having the plurality of layers, forming a second metal layer on the exposed portion of the first metal layer, removing the patterned resist laminate having the plurality of layers, and etching at least another portion of the first metal layer.

Abstract: A coil component includes a body; first and second coil portions spaced apart from each other in the body; first and second external electrodes disposed on the body to be spaced apart from each other and connected to both ends of the first coil portion; and first and second ground electrodes spaced apart from each other on the body and connected to both ends of the second coil portion.

Abstract: An apparatus of tilting a seat cushion of a vehicle, includes a tilting motor, a pinion gear, a sector gear, and a tilting link which perform the tilting operation of the seat cushion and exert a binding force in a tilted state of the seat cushion and are provided to be connected to both of one side and the other side of a seat cushion frame, and has two sector gears positioned on left and right sides and connected to each other by a connection bar so that, by strengthening a binding force of the front portion of the seat cushion, it is possible to secure the safety of passengers in the event of a collision.

Abstract: A method of manufacturing a printed circuit board a includes preparing an insulating substrate on which a first metal layer is formed, stacking a resist laminate having a plurality of layers on the first metal layer, forming an opening exposing a portion of the first metal layer by patterning the stacked resist laminate having the plurality of layers, forming a second metal layer on the exposed portion of the first metal layer, removing the patterned resist laminate having the plurality of layers, and etching at least another portion of the first metal layer.

Abstract: A method of manufacturing a printed circuit board a includes preparing an insulating substrate on which a first metal layer is formed, stacking a resist laminate having a plurality of layers on the first metal layer, forming an opening exposing a portion of the first metal layer by patterning the stacked resist laminate having the plurality of layers, forming a second metal layer on the exposed portion of the first metal layer, removing the patterned resist laminate having the plurality of layers, and etching at least another portion of the first metal layer.

Abstract: An antenna board includes a first base board unit including a first insulating layer having a first receiving groove; a first antenna board unit disposed in the first receiving groove, including a second insulating layer and a third insulating layer disposed on the second insulating layer, and further including at least one of a first patch pattern disposed on the second insulating layer and covered by the third insulating layer and a second patch pattern disposed on the third insulating layer; and a first encapsulant covering at least a portion of the first antenna board unit and filling at least a portion of the first receiving groove, wherein a dielectric constant of the second insulating layer is different from a dielectric constant of the third insulating layer.

Abstract: A method of manufacturing a printed circuit board includes: forming a resist layer; exposing first areas of the resist layer spaced apart from each other; after exposing the first areas, exposing second areas of the resist layer, the second areas being spaces between the first areas; forming first and second openings spaced apart from each other in the first and second areas by developing the resist layer; and forming a plurality of conductor patterns by filling the first and second openings with conductors.

Abstract: A printed circuit board includes a first insulating layer, a metal layer disposed on one surface of the first insulating layer, a first circuit layer disposed inside the first insulating layer and having one surface exposed to the one surface of the first insulating layer so as to be in contact with one surface of the metal layer, a second circuit layer in contact with the other surface of the metal layer, and a second insulating layer disposed on the one surface of the first insulating layer to cover the metal layer and the second circuit layer. The first and second circuit layers respectively include a metal different from the metal layer.

Abstract: An antenna board includes a first base board unit including a first insulating layer having a first receiving groove; a first antenna board unit disposed in the first receiving groove, including a second insulating layer and a third insulating layer disposed on the second insulating layer, and further including at least one of a first patch pattern disposed on the second insulating layer and covered by the third insulating layer and a second patch pattern disposed on the third insulating layer; and a first encapsulant covering at least a portion of the first antenna board unit and filling at least a portion of the first receiving groove, wherein a dielectric constant of the second insulating layer is different from a dielectric constant of the third insulating layer.

Abstract: A data storage system includes a memory device including a plurality of memory cells which are coupled to a plurality of row lines, and configured to communicate with a host device through at least one port; and a memory controller configured to select one of a first precharge policy and a second precharge policy according to a precharge control signal, and control the row lines based on access addresses for the row lines according to the selected precharge policy, wherein, under the first precharge policy, one of a first precharge scheme and a second precharge scheme is applied, and under the second precharge policy, both the first and second precharge schemes are applied at different times.

Abstract: A data storage system includes a memory device including a plurality of memory cells which are coupled to a plurality of row lines, and configured to communicate with a host device through at least one port; and a memory controller configured to select one of a first precharge policy and a second precharge policy according to a precharge control signal, and control the row lines based on access addresses for the row lines according to the selected precharge policy, wherein, under the first precharge policy, one of a first precharge scheme and a second precharge scheme is applied, and under the second precharge policy, both the first and second precharge schemes are applied at different times.

Abstract: A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.

Abstract: A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.

Abstract: A nonvolatile memory cell includes first and second interlayer insulating films which are separated from each other and are stacked sequentially, a first electrode which penetrates the first interlayer insulating film and the second interlayer insulating film, a resistance change film which is formed along a side surface of the first electrode and extends parallel to the first electrode, and a second electrode which is formed between the first interlayer insulating film and the second interlayer insulating film. The second electrode includes a conductive film which is made of metal and a diffusion preventing film which prevents diffusion of a conductive material contained in the conductive film.

Abstract: Provided are a nonvolatile memory device and a method for fabricating the same. The method includes sequentially stacking on a semiconductor substrate a first interlayer dielectric film, a first sacrificial layer, a second interlayer dielectric film, and a second sacrificial layer, forming a resistance variable layer and a first electrode penetrating the first and second interlayer dielectric films and the first and second sacrificial layers, forming an upper trench by removing a top portion of the first electrode, filling the upper trench with a channel layer, exposing a portion of a side surface of the resistance variable layer by removing the second sacrificial layer, forming an insulation layer within the channel layer, and forming a second electrode on the exposed resistance variable layer.

Abstract: Provided is a method of fabricating a nonvolatile memory device.

Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Abstract: A semiconductor device includes a first horizontal molding pattern, a horizontal electrode pattern disposed on the first horizontal molding pattern, and a second horizontal molding pattern disposed on the horizontal electrode pattern. A vertical structure extends through the horizontal patterns. The vertical structure includes a vertical electrode pattern, a data storage pattern interposed between the vertical electrode pattern and the horizontal patterns, a first buffer pattern interposed between the data storage pattern and the first molding pattern, and a second buffer pattern interposed between the data storage pattern and the second molding pattern and spaced apart from the first buffer pattern.

Abstract: Nonvolatile memory devices including a first interlayer insulating film and a second interlayer insulating film separated from each other and are stacked sequentially, a first electrode penetrating the first interlayer insulating film and the second interlayer insulating film, a resistance change film along a top surface of the first interlayer insulating film, side surfaces of the first electrode, and a bottom surface of the second interlayer insulating film, and a second electrode between the first interlayer insulating film and the second interlayer insulating film.