Abstract: A non-volatile memory device includes a lower molding layer, a horizontal interconnection line on the lower molding layer, an upper molding layer on the horizontal interconnection line, pillars extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer, and a buffer layer interposed between the pillars and the molding layers. The device also includes variable resistance material and a diode layer interposed between the pillars and the horizontal interconnection line.

Abstract: Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.

Abstract: A semiconductor device includes a first horizontal molding pattern, a horizontal electrode pattern disposed on the first horizontal molding pattern, and a second horizontal molding pattern disposed on the horizontal electrode pattern. A vertical structure extends through the horizontal patterns. The vertical structure includes a vertical electrode pattern, a data storage pattern interposed between the vertical electrode pattern and the horizontal patterns, a first buffer pattern interposed between the data storage pattern and the first molding pattern, and a second buffer pattern interposed between the data storage pattern and the second molding pattern and spaced apart from the first buffer pattern.

Abstract: Provided is a method of fabricating a nonvolatile memory device.

Abstract: Provided are a nonvolatile memory device and a method for fabricating the same. The method includes sequentially stacking on a semiconductor substrate a first interlayer dielectric film, a first sacrificial layer, a second interlayer dielectric film, and a second sacrificial layer, forming a resistance variable layer and a first electrode penetrating the first and second interlayer dielectric films and the first and second sacrificial layers, forming an upper trench by removing a top portion of the first electrode, filling the upper trench with a channel layer, exposing a portion of a side surface of the resistance variable layer by removing the second sacrificial layer, forming an insulation layer within the channel layer, and forming a second electrode on the exposed resistance variable layer.

Abstract: A non-volatile memory device includes a lower molding layer, a horizontal interconnection line on the lower molding layer, an upper molding layer on the horizontal interconnection line, pillars extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer, and a buffer layer interposed between the pillars and the molding layers. The device also includes variable resistance material and a diode layer interposed between the pillars and the horizontal interconnection line.

Abstract: A nonvolatile memory cell includes first and second interlayer insulating films which are separated from each other and are stacked sequentially, a first electrode which penetrates the first interlayer insulating film and the second interlayer insulating film, a resistance change film which is formed along a side surface of the first electrode and extends parallel to the first electrode, and a second electrode which is formed between the first interlayer insulating film and the second interlayer insulating film. The second electrode includes a conductive film which is made of metal and a diffusion preventing film which prevents diffusion of a conductive material contained in the conductive film.

Abstract: Nonvolatile memory devices including a first interlayer insulating film and a second interlayer insulating film separated from each other and are stacked sequentially, a first electrode penetrating the first interlayer insulating film and the second interlayer insulating film, a resistance change film along a top surface of the first interlayer insulating film, side surfaces of the first electrode, and a bottom surface of the second interlayer insulating film, and a second electrode between the first interlayer insulating film and the second interlayer insulating film.

Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Abstract: Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.

Abstract: In methods of manufacturing a semiconductor device, a plurality of gate structures spaced apart from each other and oxide layer patterns. A sputtering process using the oxide layer patterns as a sputtering target to connect the oxide layer patterns on the adjacent gate structures to each other is performed, so that a gap is formed between the gate structures. A volume of the gap is formed uniformly to have desired volume by controlling a thickness of the oxide layer patterns.

Abstract: A gas sensor and method thereof are provided. The example gas sensor may include first and second electrodes formed on a substrate, a carbon nanotube connecting the first and second electrodes on the substrate, a light source disposed above the carbon nanotube and an ampere meter measuring current flowing between the first and second electrodes.

Abstract: Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a charge storage layer on the tunneling insulating layer, forming a blocking insulating layer on the charge storage layer, irradiating the blocking insulating layer and/or the tunneling insulating layer with a neutral beam, and forming a gate conductive layer on the blocking insulating layer.

Abstract: In a semiconductor device including a plurality of memory units and a method of testing the same, the semiconductor device includes a plurality of memory units each comprising a plurality of input lines; and an input unit configured to provide a plurality of test signals to the input lines, respectively, included in each of the memory units in response to a test enable signal. A data input/output unit can be configured to receive Z-bit data from test equipment and to distribute the Z-bit data to the plurality of memory units in response to the test enable signal, where Z is a natural number. The data input/output unit outputs K-bit data, which are output from each of the plurality of memory units, through data input/output lines included in the plurality of memory units in response to the test enable signal, where K?Z and K is a natural number.

Abstract: A flash memory device can include a semiconductor fin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor fin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type, and a plurality of word lines extending over a top and a sidewall of the semiconductor fin to intersect the direction. The word lines overlap the first doped layer and the second doped layer to have vertical channels.

Abstract: Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a charge storage layer on the tunneling insulating layer, forming a blocking insulating layer on the charge storage layer, irradiating the blocking insulating layer and/or the tunneling insulating layer with a neutral beam, and forming a gate conductive layer on the blocking insulating layer.

Abstract: Provided are non-volatile memory devices that may realize high integration and have high reliability. A plurality of first semiconductor layers are stacked on a substrate. A plurality of second semiconductor layers are interposed between the plurality of first semiconductor layers, respectively, and are recessed from one end of each of the plurality of first semiconductor layers to define a plurality of first trenches between the plurality of first semiconductor layers. A plurality of first storage nodes are provided on surfaces of the second semiconductor layers inside the plurality of first trenches. Devices may include a plurality of first control gate electrodes that are formed on the plurality of first storage nodes to fill the plurality of first trenches.

Abstract: Nonvolatile memory transistors including active pillars having smooth side surfaces with an acute inward angle are provided. The transistor has an active pillar having smooth side surfaces with an acute inward angle and protrudes from semiconductor substrate. A gate electrode surrounds the side surfaces of the active pillar. A charge storage layer is provided between the active pillar and the gate electrode. Nonvolatile memory arrays including the transistor and related methods of fabrication are also provided.

Abstract: In a semiconductor device including a plurality of memory units and a method of testing the same, the semiconductor device includes a plurality of memory units each comprising a plurality of input lines; and an input unit configured to provide a plurality of test signals to the input lines, respectively, included in each of the memory units in response to a test enable signal. A data input/output unit can be configured to receive Z-bit data from test equipment and to distribute the Z-bit data to the plurality of memory units in response to the test enable signal, where Z is a natural number. The data input/output unit outputs K-bit data, which are output from each of the plurality of memory units, through data input/output lines included in the plurality of memory units in response to the test enable signal, where K?Z and K is a natural number.

Abstract: A flash memory device can include a semiconductor pin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor pin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type, and a plurality of word lines extending over a top and a sidewall of the semiconductor pin to intersect the direction. The word lines overlap the first doped layer and the second doped layer to have vertical channels.