Abstract: There are disclosed herein various implementations of a semiconductor component including a protrusion propagation body. The semiconductor component includes a substrate, a III-Nitride intermediate stack including the protrusion propagation body situated over the substrate, a III-Nitride buffer layer situated over the group III-V intermediate stack, and a III-Nitride device fabricated over the group III-V buffer layer. The protrusion propagation body includes at least a protrusion generating layer and two or more protrusion spreading multilayers.

Abstract: A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.

Abstract: A resistive memory device may include a resistive cell array and an on-chip resistance measurement circuit. The resistive cell array may include a plurality of resistive memory cells. The on-chip resistance measurement circuit may be configured to generate a first current and a second current greater or less than the first current based on a cell current corresponding to a cell resistance of a first memory cell of the resistive memory cells, and to generate first and second digital signals based on the first and second current, respectively.

Abstract: A resistive memory device may include first and second resistive memory cells, a reference current generator, and first and second bitline sense amplifiers. The reference current generator may be configured to apply the first and second reference currents to a first common node. A total reference current of the first reference current and the second reference current provided to the first common node may be divided into a first sensing current and a second sensing current by the first common node. The first and second sensing currents may be provided to the first and second bitline sense amplifiers by the first common node, respectively. The first and second bitline sense amplifiers may be configured to sense first data of the first resistive memory cell and second data of the second resistive memory cell based on the first and second sensing currents, respectively.

Abstract: A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.

Abstract: A resistive memory device may include first and second resistive memory cells, a reference current generator, and first and second bitline sense amplifiers. The reference current generator may be configured to apply the first and second reference currents to a first common node. A total reference current of the first reference current and the second reference current provided to the first common node may be divided into a first sensing current and a second sensing current by the first common node. The first and second sensing currents may be provided to the first and second bitline sense amplifiers by the first common node, respectively. The first and second bitline sense amplifiers may be configured to sense first data of the first resistive memory cell and second data of the second resistive memory cell based on the first and second sensing currents, respectively.

Abstract: A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.

Abstract: A resistive memory device may include a resistive cell array and an on-chip resistance measurement circuit. The resistive cell array may include a plurality of resistive memory cells. The on-chip resistance measurement circuit may be configured to generate a first current and a second current greater or less than the first current based on a cell current corresponding to a cell resistance of a first memory cell of the resistive memory cells, and to generate first and second digital signals based on the first and second current, respectively.

Abstract: A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

Abstract: Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.

Abstract: A magneto-resistive random access memory (MRAM) including an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell. The control and voltage generation unit including a command decoder configured to generate a decoding signal in response to a command output from a memory controller, and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller.

Abstract: A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.

Abstract: Example embodiments include a resistive type memory sense amplifier circuit including differential output terminals, first and second input terminals, a pre-charge section, and other components arranged so that current is re-used during at least a “set” or “amplification” stage of the sense amplifier circuit, thereby reducing overall current consumption of the circuit, and improving noise immunity. A voltage level of a high-impedance output terminal is caused to swing in response to a delta average current between a reference line current and a bit line current. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit. Also disclosed is a current mirror circuit, which can be used in conjunction with the disclosed sense amplifier circuit. In yet another embodiment, a sense amplifier circuit includes the capability of read/re-write operation.

Abstract: A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.

Abstract: A memory cell array of a nonvolatile semiconductor memory device is provided which includes a first memory cell including a first variable resistance element and a first access transistor connected to each other, and having a first node connected to a first bit line and one end of the first variable resistance element and a second node connected to a second bit line and one end of the first access transistor; and a second memory cell including a second variable resistance element and a second access transistor connected to each other, and having a first node connected to the second bit line and one end of the second variable resistance element and a second node connected to one end of the second access transistor, wherein the first and second access transistors are connected to first and second word lines, respectively.

Abstract: Example embodiments include a level shifting write driver in a sense amplifier for a resistive type memory. The write driver may include a cross-coupled latch circuit, a first output section, a second output section, and an input section. The first output section includes one or more first driving transistors to drive a first current through the first output section and not through the cross-coupled latch. The second output section includes one or more second driving transistors configured to drive a second current through the second output section and not through the cross-coupled latch. The current flows of the outputs sections are isolated from the latch circuit. In some embodiments, no two PMOS type transistors are serially connected, thereby reducing the consumption of die area. In some embodiments, a single control signal is used to operate the write driver.

Abstract: A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.

Abstract: Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.

Abstract: A magneto-resistive random access memory (MRAM) comprising an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell. The control and voltage generation unit comprising a command decoder configured to generate a decoding signal in response to a command output from a memory controller, and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller.

Abstract: A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.