Patents by Inventor Chan Kyung

Chan Kyung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110018581
    Abstract: Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal.
    Type: Application
    Filed: September 30, 2010
    Publication date: January 27, 2011
    Inventors: Sang-Soon Lim, Chan-kyung Kim
  • Patent number: 7830179
    Abstract: Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: November 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-soon Lim, Chan-kyung Kim
  • Publication number: 20100171561
    Abstract: An oscillator including: a first complementary differential amplifier (CDA) outputting a first output signal obtained by amplifying signals input to a first input terminal and a second input terminal of the first CDA; and a second CDA outputting a second output signal obtained by amplifying signals input to a first input terminal and a second input terminal of the second CDA, the second output signal having a differential phase with respect to the first output signal, wherein the first CDA may include an output terminal connected to the first input terminal and the second input terminal of the second CDA and the second CDA may include an output terminal connected to the first input terminal and the second input terminal of the first CDA.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 8, 2010
    Inventor: Chan-kyung Kim
  • Publication number: 20100171555
    Abstract: A circuit for outputting an amplified clock signal is disclosed. The circuit includes a first input terminal for inputting a first clock signal, a second input terminal for inputting a second clock signal, a first amplifier circuit for amplifying the first clock signal and outputting a first amplified clock signal at a first output terminal, and a second amplifier circuit for amplifying the second clock signal and outputting a second amplified clock signal at a second output terminal. The circuit additionally includes a level maintenance circuit connected to the first output terminal and the second output terminal. The circuit further includes an output circuit connected to the first output terminal and the second output terminal and configured to output a further amplified clock signal based on the first amplified clock signal and the second amplified clock signal. The level maintenance circuit is configured to reduce duty distortion in the further amplified clock signal.
    Type: Application
    Filed: January 4, 2010
    Publication date: July 8, 2010
    Inventor: Chan-kyung Kim
  • Publication number: 20100124137
    Abstract: A voltage-controlled oscillator comprises a first oscillator and a second oscillator. The first oscillator may generate a plurality of intermediate clock signals at a plurality of first nodes, multiply connected to a plurality of first ring shape circuits, in response to a control voltage. The plurality of intermediate clock signals may have a different phase from each other and a same phase difference with each other. The second oscillator may generate a plurality of output clock signals at a plurality of second nodes, multiply connected to a plurality of second ring shape circuits, by changing a voltage level of the intermediate clock signals. The plurality of second ring shape circuits may pass the plurality of first nodes.
    Type: Application
    Filed: November 9, 2009
    Publication date: May 20, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Chan-Kyung Kim
  • Publication number: 20100073097
    Abstract: One embodiment of the oscillator includes a first starved inverter and a second starved inverter. An inner inverter of the second starved inverter is cross-coupled to an inner inverter of the first starved inverter. The oscillator further includes a first inverter connected to output of the inner inverter of the first starved inverter, and a second inverter connected to output of the inner inverter of the second starved inverter.
    Type: Application
    Filed: January 30, 2009
    Publication date: March 25, 2010
    Inventor: Chan-kyung Kim
  • Patent number: 7683726
    Abstract: A voltage controlled oscillator (VCO) is provided. The VCO may include a first ring oscillation circuit that may have a plurality of delay cells and may output first differential oscillation signals, and a second ring oscillation circuit that may have a plurality of delay cells and may output second differential oscillation signals. The delay cells of the first ring oscillation circuit may be respectively cross-coupled to the corresponding delay cells of the second ring oscillation circuit. Each of the delay cells may include a differential amplification circuit that may output a first differential signal based on a first control signal, and a negative resistance circuit that may be connected in parallel to a pair of output terminals of the differential amplification circuit, may receive a second differential signal, may adjust the phase of the first differential signal based on a second control signal, and may then output the first differential signal.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan Kyung Kim
  • Patent number: 7671651
    Abstract: A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: March 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-kyung Kim
  • Patent number: 7656725
    Abstract: A memory device compensates for delay time variations among multi-bit data. The device includes a first stage and a second stage of data storage units. The first stage of data storage units store first to nth data bits in response to a latch clock signal. The second stage of data storage units store the first to nth data contents output from the first stage of data storage units in response to a reference clock signal. The latch clock signal is obtained by delaying the reference clock signal. The latch clock signal includes first to nth sub latch signals. The sub latch signals are generated at different times according to propagation delay time periods of the corresponding first to nth data contents.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: February 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-kyung Kim
  • Patent number: 7603535
    Abstract: A semiconductor memory device includes a memory cell core having a plurality of memory cells; a data input/output circuit unit, which sets an input/output data width in response to input/output control signals and inputs/outputs data signals through at least some of a plurality of input/output pads; a pipelined circuit unit, which is connected to the data input/output circuit unit through input/output lines and transmits the data signals between the memory cell core and the data input/output circuit unit in synchronization with predetermined clock signals through an input/output path selected in response to pipeline enable signals; and a plurality of selection units, which are connected to the input/output lines through external common data lines and connect some of the input/output lines to the data input/output circuit unit in response to selection control signals.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: October 13, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hwan Choi, Chan-kyung Kim
  • Patent number: 7581881
    Abstract: Provided are a temperature sensor using a ring oscillator and temperature detection method using the same. One embodiment of the temperature sensor includes a first pulse generator, a second pulse generator, and a counter. The first pulse generator includes a first ring oscillator and generates a first clock signal having a variable period according to a change in temperature. The second pulse generator includes a second ring oscillator and generates a second clock signal having a fixed period. The counter counts a pulse width of the first clock signal as a function of a pulse width of the second clock signal and generates a temperature code.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: September 1, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Kyung Kim, Young-Hyun Jun
  • Patent number: 7566908
    Abstract: Light emitting diodes (LEDs) with various electrode structures which preferably provide increased performance. In some embodiments the LEDs are GaN-based and in some embodiments the LEDs are ZnO-based, with a sapphire substrate or a ZnO substrate. In some embodiments the LEDs are hybrid GaN-based ZnO based LEDs.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: July 28, 2009
    Inventors: Yongsheng Zhao, Jin-Joo Song, Chan Kyung Choi
  • Publication number: 20090134908
    Abstract: Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal.
    Type: Application
    Filed: November 24, 2008
    Publication date: May 28, 2009
    Inventors: Sang-soon Lim, Chan-kyung Kim
  • Patent number: 7534035
    Abstract: Provided are a temperature sensor for generating a sectional temperature code and sectional temperature detection method. In one embodiment, the temperature sensor includes a plurality of serially connected fixed delay cells inputting a temperature detection signal and delaying the temperature detection signal, a variable delay cell inputting the temperature detection signal and delaying the temperature detection signal; and a sectional discrimination logic unit latching outputs of the fixed delay cells in response to the variable delay cells and generating the sectional temperature code. The sectional discrimination logic unit discriminates the sectional temperatures based on temperatures where an output of the variable delay cell meets each of outputs of the fixed delay cells according to the change in the temperature, and generates temperature codes corresponding to the sectional temperatures.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: May 19, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-Kyung Kim
  • Patent number: 7501870
    Abstract: A duty cycle correction circuit may include an error corrector adapted to correct duty cycles of first differential analog clock signals input to a pair of input terminals based on duty cycle correction signals input to a pair of control terminals and to output second differential analog clock signals having corrected duty cycles through a pair of output terminals, an analog to digital buffer adapted to convert the second differential analog clock signals to differential digital clock signals, a duty error detector adapted to detect duty cycles of the differential digital clock signals and to output a N bit digital signal, and a duty error correction signal generator adapted to output differential control current signals having current gains controlled based on the second differential analog clock signals and the N bit digital signal to the pair of control terminals as the duty cycle correction signals.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: March 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Su Choi, Chan Kyung Kim
  • Publication number: 20080252386
    Abstract: A voltage controlled oscillator (VCO) is provided. The VCO may include a first ring oscillation circuit that may have a plurality of delay cells and may output first differential oscillation signals, and a second ring oscillation circuit that may have a plurality of delay cells and may output second differential oscillation signals. The delay cells of the first ring oscillation circuit may be respectively cross-coupled to the corresponding delay cells of the second ring oscillation circuit. Each of the delay cells may include a differential amplification circuit that may output a first differential signal based on a first control signal, and a negative resistance circuit that may be connected in parallel to a pair of output terminals of the differential amplification circuit, may receive a second differential signal, may adjust the phase of the first differential signal based on a second control signal, and may then output the first differential signal.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 16, 2008
    Inventor: Chan Kyung Kim
  • Publication number: 20080219333
    Abstract: A signal transceiver may include three transmission lines, a signal transmission unit, and/or a signal reception unit. The signal transmission unit may be configured encode first through third transmission data to generate first through third data and transmit the first through third data through the three transmission lines. The signal transmission unit may be configured to generate each of the first through third data at one of four or more voltage level. The signal reception unit may be configured to receive the first through third data and monitor voltage differences between the first through third data to restore the first through third data into first through third reception data.
    Type: Application
    Filed: February 15, 2008
    Publication date: September 11, 2008
    Inventor: Chan-kyung Kim
  • Patent number: 7358774
    Abstract: In an output driver circuit and method, a control circuit generates a control signal in response to a current internal data signal. An output driver generates an output data signal in response to the control signal. A pre-emphasis circuit adjusts a current flowing through a node having the control signal generated thereon in response to a previous internal data signal. The pre-emphasis circuit may also adjust the output signal in response to the previous internal data signal.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: April 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-Kyung Kim
  • Publication number: 20080049793
    Abstract: A method of transmitting/receiving a packet using a hybrid automatic repeat request in the mobile communication system is disclosed. The packet data transmitting method includes transmitting at least one sub packet divided from plurality of encoded packets generated by repeating a bit stream that is made by encoding information desired to be transmitted with ? rate turbo encoder, and transmission start point information of the sub packet through the sub packet identifier field on the accompanying control channel.
    Type: Application
    Filed: October 29, 2007
    Publication date: February 28, 2008
    Inventors: Young Yun, Young Lee, Ki Kim, Soon Kwon, Suk Yoon, Jong An, Chan Kyung
  • Publication number: 20080043776
    Abstract: A method of transmitting/receiving a packet using a hybrid automatic repeat request in the mobile communication system is disclosed. The packet data transmitting method includes transmitting at least one sub packet divided from plurality of encoded packets generated by repeating a bit stream that is made by encoding information desired to be transmitted with 1/5 rate turbo encoder, and transmission start point information of the sub packet through the sub packet identifier field on the accompanying control channel.
    Type: Application
    Filed: October 29, 2007
    Publication date: February 21, 2008
    Inventors: Young Woo YUN, Young LEE, Ki KIM, Soon KWON, Suk YOON, Jong AN, Chan KYUNG