Patents by Inventor Chan Li
Chan Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240131585Abstract: A method and an apparatus for forming powder. The formed powder may include an alloy of powder that can be used in additively manufacturing and powder metallurgy applications to create structures. The method and apparatus may deliver a source material having a first material composition, melt the source material to form a molten source material, vibrate a substate structure, the substrate structure including a substrate material having a substrate material composition, apply the molten source material to the vibrating substrate structure to obtain a powder, where a portion of the substrate material is selectively added to the molten source material such that the powder has a second material composition different than the first material composition, and control the second material composition of the powder based on the first material composition and the substrate material composition.Type: ApplicationFiled: October 19, 2023Publication date: April 25, 2024Inventors: Chan Cheong PUN, Mu Li
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Publication number: 20240131586Abstract: Alloyed metals, and techniques for creating parts from alloyed metals, are disclosed. An apparatus in accordance with an aspect of the present disclosure comprises an alloy. An additive manufacturing alloy in accordance with the present disclosure may comprise magnesium (Mg) that is between 2.0 and 5.3% by weight, manganese (Mn) that is between 0.01 and 4.0% by weight, silicon (Si) that is between 0.1 and 1.5% by weight, zirconium (Zr) that is between 0.01 and 2.0% by weight, and aluminum (Al). In some cases, the alloy such as described in the previous sentence might not include Mg.Type: ApplicationFiled: October 16, 2023Publication date: April 25, 2024Inventors: Mu LI, Keith Mathew MERTAN, Chan Cheong PUN, Michael Thomas KENWORTHY
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Publication number: 20240119213Abstract: A method includes designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track of a plurality of routing tracks within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines, and the reserved routing track is free of the signal lines. The method includes placing a first cell and a second cell of the plurality of cells in a layout of the semiconductor device. The method includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell. The method includes adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track other than the reserved routing track.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Jian-Sing LI, Jung-Chan YANG, Ting Yu CHEN, Ting-Wei CHIANG
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Patent number: 11955507Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.Type: GrantFiled: September 9, 2021Date of Patent: April 9, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
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Publication number: 20240084455Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.Type: ApplicationFiled: February 8, 2023Publication date: March 14, 2024Inventors: Che Wei YANG, Chih Cheng SHIH, Kuo Liang LU, Yu JIANG, Sheng-Chan LI, Kuo-Ming WU, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
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Method for positioning vertebra in CT image, apparatus, device, and computer readable storage medium
Patent number: 11928782Abstract: The present disclosure provides a method of positioning vertebra in a CT image, an apparatus, a computer device, and a computer readable storage medium. The method includes: pre-processing vertebra CT image data; inputting the pre-processed vertebra CT image data into a pre-trained neural network to obtain regression results of heat maps of key points corresponding to the pre-processed vertebra CT image data; regressing of 3D heat maps corresponding to the positions of the key points of the vertebra mass center based on the regression results of the heat maps of the key points and the pre-processed vertebra CT image data; serving 3D heat maps corresponding to the positions of the key points of the vertebra mass center as labels, and networked regressing 3D heat map information to position the vertebra. Effects caused by scanning machine difference and scanning noise are avoided, and the vertebra with complex forms is accurately positioned.Type: GrantFiled: October 30, 2020Date of Patent: March 12, 2024Assignee: PING AN TECHNOLOGY (SHENZHEN) CO., LTD.Inventors: Chan Zeng, Ge Li, Guanju Cheng, Peng Gao, Guotong Xie -
Publication number: 20240079268Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
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Patent number: 11923205Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.Type: GrantFiled: December 17, 2021Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
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Publication number: 20240071988Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming an initial barrier material layer and a conductive layer on an upper surface of the dielectric layer and in the hole; removing part of the initial barrier material layer and part of the conductive layer to form a barrier material layer and a via element in the hole respectively and expose the upper surface of the dielectric layer. An upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.Type: ApplicationFiled: October 11, 2022Publication date: February 29, 2024Inventors: Kun-Ju LI, Hsin-Jung LIU, Wei-Xin GAO, Jhih-Yuan CHEN, Ang CHAN, Chau-Chung HOU
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Patent number: 11908878Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.Type: GrantFiled: May 24, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
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Patent number: 11901387Abstract: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.Type: GrantFiled: July 7, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
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Publication number: 20240043533Abstract: The present disclosure provides binding agents, such as antibodies, that specifically bind ILT3, including human ILT3, as well as compositions comprising the binding agents, and methods of their use. The disclosure also provides related polynucleotides and vectors encoding the binding agents and cells comprising the binding agents.Type: ApplicationFiled: August 2, 2023Publication date: February 8, 2024Inventors: Suzanne Christine Crawley, Jer-Yuan Hsu, Daniel David Kaplan, Betty Chan Li, Vicky Yi-Bing Lin, Seth Malmersjö, Kevin James Paavola, Julie Michelle Roda, Yan Wang
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Publication number: 20240030258Abstract: Doping a liner of a trench isolation structure with fluorine reduces dark current from a photodiode. For example, the fluorine may be added to a passivation layer surrounding a backside deep trench isolation structure. As a result, sensitivity of the photodiode is increased. Additionally, breakdown voltage of the photodiode is increased, and a quantity of white pixels in a pixel array including the photodiode are reduced.Type: ApplicationFiled: July 22, 2022Publication date: January 25, 2024Inventors: Chung-Liang CHENG, Sheng-Chan LI, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
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Patent number: 11869916Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.Type: GrantFiled: November 13, 2020Date of Patent: January 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Wei Liang, Sheng-Chau Chen, Hsun-Chung Kuang, Sheng-Chan Li
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Patent number: 11862515Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.Type: GrantFiled: August 4, 2022Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
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Publication number: 20230395631Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.Type: ApplicationFiled: August 9, 2023Publication date: December 7, 2023Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
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Publication number: 20230378225Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.Type: ApplicationFiled: August 4, 2023Publication date: November 23, 2023Inventors: Chin-Wei Liang, Sheng-Chau Chen, Hsun-Chung Kuang, Sheng-Chan Li
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Publication number: 20230369368Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a lower reflectivity than the first material.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Inventors: Che Wei Yang, Sheng-Chan Li, Tsun-Kai Tsao, Chih-Cheng Shih, Sheng-Chau Chen, Cheng-Yuan Tsai
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Publication number: 20230369516Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating. wherein the composite etch stop mask layer includes a silicon nitride layer and a stressed layer. A percentage of Si—H bonds in the silicon nitride layer is greater than a percentage of Si—H bonds in the stressed layer.Type: ApplicationFiled: July 18, 2023Publication date: November 16, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Han LIN, Chao-Ching CHANG, Yi-Ming LIN, Yen-Ting CHOU, Yen-Chang CHEN, Sheng-Chan LI, Cheng-Hsien CHOU
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Publication number: 20230369023Abstract: A tunable plasma exclusion zone in semiconductor fabrication is provided. A semiconductor wafer is provided within a chamber of a plasma processing apparatus between a first plasma electrode and a second plasma electrode. A plasma is generated from a process gas within the chamber and an electric field between the first plasma electrode and the second plasma electrode. The plasma is at least partially excluded from an edge region of the semiconductor wafer by a plasma exclusion zone (PEZ) ring within the chamber. The plasma may be tuned toward a center of the semiconductor wafer by electrically coupling an electrode ring of the PEZ ring to a voltage potential.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Che Wei Yang, Chih Cheng Shih, Sheng-Chan Li, Cheng-Yuan Tsai, Sheng-Chau Chen