Patents by Inventor Chan Li

Chan Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12272715
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Hau-Yi Hsiao, Che Wei Yang, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 12266579
    Abstract: A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a gap sensor configured to generate sensor signals indicative of a gap between the wafer and the top plate. The system includes a control system configured to adjust the gap during the thin-film deposition process responsive to the sensor signals.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chan Li, Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Publication number: 20250105056
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Publication number: 20250098350
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate having an image sensor region arranged between sidewalls of the substrate that form one or more trenches. One or more dielectric materials are arranged along the sidewalls of the substrate that form the one or more trenches. A reflective region is disposed within the one or more trenches and laterally surrounded by the one or more dielectric materials. The reflective region includes a plurality of reflective portions that are arranged at different vertical positions within the reflective region and that have different reflective properties.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Keng-Yu Chou, Yeur-Luen Tu
  • Patent number: 12240899
    Abstract: The present disclosure provides binding agents, such as antibodies, that specifically bind LAIR-1, including human LAIR-1, as well as compositions comprising the binding agents, and methods of their use. The disclosure also provides related polynucleotides and vectors encoding the binding agents and cells comprising the binding agents.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 4, 2025
    Assignee: NGM Biopharmaceuticals, Inc.
    Inventors: Suzanne Christine Crawley, Bin Fan, Betty Chan Li, Lee Benjamin Rivera, James Robert Sissons, Jonathan Sitrin, Yan Wang, Xuan Zhao
  • Patent number: 12211741
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Patent number: 12199120
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a pixel region arranged between one or more trenches formed by sidewalls of the substrate. One or more dielectric materials are arranged along the sidewalls of the substrate forming the one or more trenches. A conductive material is disposed within the one or more trenches. The conductive material is electrically coupled to an interconnect disposed within a dielectric arranged on the substrate.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Keng-Yu Chou, Yeur-Luen Tu
  • Patent number: 12187796
    Abstract: The present disclosure provides binding agents, such as antibodies, that specifically bind ILT3, including human ILT3, as well as compositions comprising the binding agents, and methods of their use. The disclosure also provides related polynucleotides and vectors encoding the binding agents and cells comprising the binding agents.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: January 7, 2025
    Assignee: NGM Biopharmaceuticals, Inc.
    Inventors: Suzanne Christine Crawley, Jer-Yuan Hsu, Daniel David Kaplan, Betty Chan Li, Vicky Yi-Bing Lin, Seth Malmersjö, Kevin James Paavola, Julie Michelle Roda, Yan Wang
  • Patent number: 12176370
    Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
  • Publication number: 20240395843
    Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 28, 2024
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
  • Patent number: 12154927
    Abstract: A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Ting Chiang, Chun-Yuan Chen, Hsiao-Hui Tseng, Sheng-Chan Li, Yu-Jen Wang, Wei Chuang Wu, Shyh-Fann Ting, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20240387299
    Abstract: A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a gap sensor configured to generate sensor signals indicative of a gap between the wafer and the top plate. The system includes a control system configured to adjust the gap during the thin-film deposition process responsive to the sensor signals.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Sheng-Chan LI, Sheng-Chau CHEN, Cheng-Hsien CHOU, Cheng-Yuan TSAI
  • Publication number: 20240387148
    Abstract: A tunable plasma exclusion zone in semiconductor fabrication is provided. A semiconductor wafer is provided within a chamber of a plasma processing apparatus between a first plasma electrode and a second plasma electrode. A plasma is generated from a process gas within the chamber and an electric field between the first plasma electrode and the second plasma electrode. The plasma is at least partially excluded from an edge region of the semiconductor wafer by a plasma exclusion zone (PEZ) ring within the chamber. The plasma may be tuned toward a center of the semiconductor wafer by electrically coupling an electrode ring of the PEZ ring to a voltage potential.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Che Wei Yang, Chih Cheng Shih, Sheng-Chan Li, Cheng-Yuan Tsai, Sheng-Chau Chen
  • Publication number: 20240379721
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Sheng-Chan Li, Hau-Yi Hsiao, Che Wei Yang, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20240379727
    Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Chi-Ming LU, Yao-Hsiang LIANG, Sheng-Chan LI, Jung-Chih TSAO, Chih-Hui HUANG
  • Patent number: 12142628
    Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chi-Ming Lu, Chih-Hui Huang, Sheng-Chan Li, Jung-Chih Tsao, Yao-Hsiang Liang
  • Publication number: 20240368925
    Abstract: A handcuff structure, comprising a lock shell, a lock cover, a movable lock ring and a key; the side of the lock shell close to the lock cover is provided with a lock box; the inside of the lock box is provided with a rotating wheel, and the center of the rotating wheel is provided with a rotating shaft; one end of the rotating shaft extends into a first shaft hole at the bottom of the lock box, and the other end of the rotating shaft extends into a second shaft hole at the bottom of the lock cover; the first shaft hole and the second shaft hole are coaxially arranged. The invention can effectively prevent prisoners from opening handcuffs through wires, needles, wooden sticks and other items, avoid criminals from escaping, and improve the overall locking effect of handcuffs.
    Type: Application
    Filed: April 30, 2024
    Publication date: November 7, 2024
    Inventors: Jianyi Liu, Chan Li, Yu Liu, Xiaoying Wang, Quanxi Liu
  • Publication number: 20240363652
    Abstract: A deep trench capacitor structure may include a metal-insulator-metal structure having an insulator layer between opposing conductive electrode layers. The deep trench capacitor structure may extend through a plurality of dielectric layers in a semiconductor device. The conductive electrode layers and the insulator layer may extend laterally into the dielectric layers. The lateral extensions of the conductive electrode layers and the insulator layer into the dielectric layers may be referred to as fin portions of the capacitor structure. The fin portions may extend laterally outward from a central portion (e.g., a trench portion) of the deep trench capacitor structure. The fin portions of the deep trench capacitor structure enable the surface area of the conductive electrode layers to be increased, which may increase the capacitance of the deep trench capacitor structure with minimal increase to the overall footprint of the deep trench capacitor structure.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Chao-Hsuan CHANG, Hsiu-Yun LIEN, Ming HUNG, Tung-I LIN, Chun CHANG, Chao-Ching CHANG, Sheng-Chan LI, Sheng-Chau CHEN
  • Publication number: 20240363469
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure has a plurality of interconnects disposed within a dielectric structure. A dielectric material is along a sidewall of the interconnect structure. The dielectric material extends to within cracks in the sidewall of the dielectric structure.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Publication number: 20240351374
    Abstract: A bicycle rear-wheel drive mechanism comprises a fixed shaft, a hollow toothed disc shaft, a wheel shaft, a sprocket shaft, an end cap and pin posts, the hollow toothed disc shaft is composed of a shaft cylinder and a toothed disc arranged at one end of the shaft cylinder, the toothed disc is provided with an array of semi-circular slots located at the edge of the disc body; in this design, the structure is stronger, the torque transmitted is greater, and the driving ability is stronger; replacing the original ball bearings used in bicycles with standardized tapered roller bearings allows the mechanism to be adjusted to the optimal axial and radial positions after installation, while also improving sealing performance and durability.
    Type: Application
    Filed: April 18, 2024
    Publication date: October 24, 2024
    Inventors: Quanxi Liu, Xiaoying Wang, Yu Liu, Nianguo Wang, Jianyi Liu, Chan Li, Qing Liu