Patents by Inventor Chan Li

Chan Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220157875
    Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Inventors: Chin-Wei Liang, Sheng-Chau Chen, Hsun-Chung Kuang, Sheng-Chan Li
  • Patent number: 11335817
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han Lin, Chao-Ching Chang, Yi-Ming Lin, Yen-Ting Chou, Yen-Chang Chen, Sheng-Chan Li, Cheng-Hsien Chou
  • Publication number: 20220115421
    Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 14, 2022
    Inventors: Tsung-Wei HUANG, Chao-Ching CHANG, Yun-Wei CHENG, Chih-Lung CHENG, Yen-Chang CHEN, Wen-Jen TSAI, Cheng Han LIN, Yu-Hsun CHIH, Sheng-Chan LI, Sheng-Chau CHEN
  • Publication number: 20220115317
    Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.
    Type: Application
    Filed: October 13, 2020
    Publication date: April 14, 2022
    Inventors: Paul YANG, Tsun-Kai TSAO, Sheng-Chau CHEN, Sheng-Chan LI, Cheng-Yuan TSAI
  • Publication number: 20220068745
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having an upper surface and a recessed surface extending in a closed loop around the upper surface. The recessed surface is vertically between the upper surface and a lower surface of the first substrate opposing the upper surface. A first plurality of interconnects are disposed within a first dielectric structure on the upper surface. A dielectric protection layer is over the recessed surface, along a sidewall of the first dielectric structure, and along a sidewall of the first substrate. The first substrate extends from directly below the dielectric protection layer to laterally outside of the dielectric protection layer.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 3, 2022
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Publication number: 20220041711
    Abstract: The present disclosure provides binding agents, such as antibodies, that specifically bind LAIR-1, including human LAIR-1, as well as compositions comprising the binding agents, and methods of their use. The disclosure also provides related polynucleotides and vectors encoding the binding agents and cells comprising the binding agents.
    Type: Application
    Filed: June 21, 2021
    Publication date: February 10, 2022
    Inventors: Suzanne Christine Crawley, Bin Fan, Betty Chan Li, Lee Benjamin Rivera, James Robert Sissons, Jonathan Sitrin, Yan Wang, Xuan Zhao
  • Patent number: 11235563
    Abstract: A resin composition is provided. The resin composition includes a styrene-acrylonitrile based copolymer of 75 parts by weight to 90 parts by weight and rubber particles of 10 parts by weight to 25 parts by weight. The resin composition includes an oligomer trimer. The oligomer trimer includes at least one monomer unit selected from the group consisting of a styrene based monomer unit and an acrylonitrile based monomer unit. Wherein, a residual acrylonitrile based monomer is less than 5 ppm of the total weight of the resin composition. The ratio of the peak area of acetophenone to the peak area of air for the resin composition as analyzed by a thermal desorption gas chromatography mass spectrometer (TD-GC-MS) is 100 to 300.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 1, 2022
    Assignee: CHIMEI CORPORATION
    Inventors: Chan-Li Hsueh, Shih-Wei Huang, Wen-Yi Su
  • Patent number: 11230472
    Abstract: The present invention refers to the field of flue gas purification, which discloses a method and apparatus for capturing carbon dioxide and producing sulfuric acid by sodium bisulfate; using a three-format electrodialysis apparatus to convert the desulfurized by-product NaHSO4 into H2SO4 while capturing CO2 in the flue gas in the cathode chamber. Under the action of electric field drive and ion exchange membrane, HSO4? enters the anode chamber to generate H2SO4 and is concentrated, and Na+ enters the cathode chamber to generate NaOH; the flue gas containing CO2 to be treated is introduced from the cathode chamber and absorbed by NaOH. The invention provides a simple, green, and economic proceeding method to capture the carbon dioxide in the flue gas during the comprehensive utilization of sodium bisulfate solution, which is of better environmental benefits and improvement of the flue gas treatment technology and reducing the pressure of desulfurization gypsum treatment.
    Type: Grant
    Filed: July 18, 2020
    Date of Patent: January 25, 2022
    Inventors: Ping Ning, Bo Li, Chuan Wang, Kai Li, Xin Song, Ruosong Xie, Lijuan Jia, Xia Wang, Guangfei Qu, Chan Li
  • Publication number: 20210371282
    Abstract: The present invention refers to the field of flue gas purification, which discloses a method and apparatus for capturing carbon dioxide and producing sulfuric acid by sodium bisulfate; using a three-format electrodialysis apparatus to convert the desulfurized by-product NaHSO4 into H2SO4 while capturing CO2 in the flue gas in the cathode chamber. Under the action of electric field drive and ion exchange membrane, HSO4? enters the anode chamber to generate H2SO4 and is concentrated, and Na+ enters the cathode chamber to generate NaOH; the flue gas containing CO2 to be treated is introduced from the cathode chamber and absorbed by NaOH. The invention provides a simple, green, and economic proceeding method to capture the carbon dioxide in the flue gas during the comprehensive utilization of sodium bisulfate solution, which is of better environmental benefits and improvement of the flue gas treatment technology and reducing the pressure of desulfurization gypsum treatment.
    Type: Application
    Filed: July 18, 2020
    Publication date: December 2, 2021
    Inventors: PING NING, BO LI, CHUAN WANG, KAI LI, XIN SONG, RUOSONG XIE, LIJUAN JIA, XIA WANG, GUANGFEI QU, CHAN LI
  • Patent number: 11189654
    Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.
    Type: Grant
    Filed: June 14, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Chia-Hsing Chou, Yi-Ming Lin, Min-Hui Lin, Chin-Szu Lee
  • Patent number: 11152276
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Patent number: 11139210
    Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Chih-Hui Huang, Kuo-Ming Wu
  • Publication number: 20210221887
    Abstract: The present disclosure provides binding agents, such as antibodies, that specifically bind ILT3, including human ILT3, as well as compositions comprising the binding agents, and methods of their use. The disclosure also provides related polynucleotides and vectors encoding the binding agents and cells comprising the binding agents.
    Type: Application
    Filed: December 17, 2020
    Publication date: July 22, 2021
    Inventors: Suzanne Christine Crawley, Jer-Yuan Hsu, Daniel David Kaplan, Betty Chan Li, Vicky Yi-Bing Lin, Seth Malmersjö, Kevin James Paavola, Julie Michelle Roda, Yan Wang
  • Publication number: 20210225919
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a photodetector arranged within a substrate. The substrate has surfaces defining one or more protrusions arranged along a first side of the substrate over the photodetector. One or more isolation structures are arranged within one or more trenches defined by sidewalls of the substrate arranged on opposing sides of the photodetector. The one or more trenches extend from the first side of the substrate to within the substrate. The one or more isolation structures respectively include a reflective medium configured to reflect electromagnetic radiation.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 22, 2021
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Keng-Yu Chou, Yeur-Luen Tu
  • Patent number: 11041242
    Abstract: A gas shower head includes a plate, a plurality of central holes disposed in a central region of the plate, and a plurality of peripheral holes disposed in a peripheral region of the plate. The central holes are configured to form a first portion of a material film, and the peripheral holes are configured to form a second portion of the material film. A hole density in the peripheral region is greater than a hole density in the central region. The first portion of the material film includes a first thickness corresponding to the hole density in central region, and the second portion of the material film includes a second thickness corresponding to the hole density in peripheral region and greater than the first thickness.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Hui Huang, Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Publication number: 20210134663
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Application
    Filed: September 30, 2020
    Publication date: May 6, 2021
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Publication number: 20210134694
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Application
    Filed: February 10, 2020
    Publication date: May 6, 2021
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Patent number: 10998364
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes an image sensing element arranged within a substrate. One or more isolation structures are arranged within one or more trenches disposed on opposing sides of the image sensing element. The one or more isolation structures extend from a first surface of the substrate to within the substrate. The one or more isolation structures respectively include a reflective element configured to reflect electromagnetic radiation.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Keng-Yu Chou, Yeur-Luen Tu
  • Publication number: 20210115133
    Abstract: The present disclosure provides binding proteins, such as antibodies, that bind beta klotho, including human beta klotho, and methods of their use.
    Type: Application
    Filed: August 28, 2020
    Publication date: April 22, 2021
    Inventors: Kalyani Mondal, Betty Chan Li, Yu Chen, Taruna Arora, Hugo Matern, Wenyan Shen
  • Publication number: 20210050460
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
    Type: Application
    Filed: April 9, 2020
    Publication date: February 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han LIN, Chao-Ching CHANG, Yi-Ming LIN, Yen-Ting CHOU, Yen-Chang CHEN, Sheng-Chan LI, Cheng-Hsien CHOU