Patents by Inventor Chan Li

Chan Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369023
    Abstract: A tunable plasma exclusion zone in semiconductor fabrication is provided. A semiconductor wafer is provided within a chamber of a plasma processing apparatus between a first plasma electrode and a second plasma electrode. A plasma is generated from a process gas within the chamber and an electric field between the first plasma electrode and the second plasma electrode. The plasma is at least partially excluded from an edge region of the semiconductor wafer by a plasma exclusion zone (PEZ) ring within the chamber. The plasma may be tuned toward a center of the semiconductor wafer by electrically coupling an electrode ring of the PEZ ring to a voltage potential.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Inventors: Che Wei Yang, Chih Cheng Shih, Sheng-Chan Li, Cheng-Yuan Tsai, Sheng-Chau Chen
  • Publication number: 20230343817
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Inventors: Alexander Kalnitsky, Ru-Liang Lee, Ming Chyi Liu, Sheng-Chan Li, Sheng-Chau Chen
  • Publication number: 20230317541
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Publication number: 20230299105
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a pixel region arranged between one or more trenches formed by sidewalls of the substrate. One or more dielectric materials are arranged along the sidewalls of the substrate forming the one or more trenches. A conductive material is disposed within the one or more trenches. The conductive material is electrically coupled to an interconnect disposed within a dielectric arranged on the substrate.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Keng-Yu Chou, Yeur-Luen Tu
  • Patent number: 11760802
    Abstract: The present disclosure provides binding agents, such as antibodies, that specifically bind ILT3, including human ILT3, as well as compositions comprising the binding agents, and methods of their use. The disclosure also provides related polynucleotides and vectors encoding the binding agents and cells comprising the binding agents.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: September 19, 2023
    Assignee: NGM Biopharmaceuticals, Inc.
    Inventors: Suzanne Christine Crawley, Jer-Yuan Hsu, Daniel David Kaplan, Betty Chan Li, Vicky Yi-Bing Lin, Seth Malmersjö, Kevin James Paavola, Julie Michelle Roda, Yan Wang
  • Publication number: 20230290672
    Abstract: In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.
    Type: Application
    Filed: May 19, 2023
    Publication date: September 14, 2023
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Tzu-Jui Wang, Sheng-Chan Li
  • Patent number: 11749760
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han Lin, Chao-Ching Chang, Yi-Ming Lin, Yen-Ting Chou, Yen-Chang Chen, Sheng-Chan Li, Cheng-Hsien Chou
  • Publication number: 20230275064
    Abstract: Various embodiments of the present disclosure are directed towards a processing tool. The processing tool includes a housing structure defining a chamber. A first plate is disposed in the chamber. A first plasma exclusion zone (PEZ) ring is disposed on the first plate. A second plate is disposed in the chamber and underlies the first plate. A second PEZ ring is disposed on the second plate. The second PEZ ring comprises a PEZ ring notch that extends inwardly from a circumferential edge of the second PEZ ring.
    Type: Application
    Filed: May 3, 2023
    Publication date: August 31, 2023
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20230268367
    Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: Tsung-Wei HUANG, Chao-Ching CHANG, Yun-Wei CHENG, Chih-Lung CHENG, Yen-Chang CHEN, Wen-Jen TSAI, Cheng Han LIN, Yu-Hsun CHIH, Sheng-Chan LI, Sheng-Chau CHEN
  • Patent number: 11735624
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Alexander Kalnitsky, Ru-Liang Lee, Ming Chyi Liu, Sheng-Chan Li, Sheng-Chau Chen
  • Publication number: 20230256070
    Abstract: The present disclosure provides binding proteins, such as antibodies, that bind beta klotho, including human beta klotho, and methods of their use.
    Type: Application
    Filed: January 12, 2023
    Publication date: August 17, 2023
    Inventors: Kalyani Mondal, Betty Chan Li, Yu Chen, Taruna Arora, Hugo Matern, Wenyan Shen
  • Patent number: 11715674
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having an upper surface and a recessed surface extending in a closed loop around the upper surface. The recessed surface is vertically between the upper surface and a lower surface of the first substrate opposing the upper surface. A first plurality of interconnects are disposed within a first dielectric structure on the upper surface. A dielectric protection layer is over the recessed surface, along a sidewall of the first dielectric structure, and along a sidewall of the first substrate. The first substrate extends from directly below the dielectric protection layer to laterally outside of the dielectric protection layer.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Patent number: 11705470
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a photodetector arranged within a substrate. The substrate has surfaces defining one or more protrusions arranged along a first side of the substrate over the photodetector. One or more isolation structures are arranged within one or more trenches defined by sidewalls of the substrate arranged on opposing sides of the photodetector. The one or more trenches extend from the first side of the substrate to within the substrate. The one or more isolation structures respectively include a reflective medium configured to reflect electromagnetic radiation.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Keng-Yu Chou, Yeur-Luen Tu
  • Patent number: 11705360
    Abstract: In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Tzu-Jui Wang, Sheng-Chan Li
  • Publication number: 20230207448
    Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 29, 2023
    Inventors: Paul YANG, Tsun-Kai TSAO, Sheng-Chau CHEN, Sheng-Chan LI, Cheng-Yuan TSAI
  • Patent number: 11682652
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 11667708
    Abstract: The present disclosure provides binding proteins, such as antibodies, and binding fragments thereof, that bind beta klotho, including human beta klotho, and exemplary specific sequences of their complementarity determining regions, variable regions, heavy chains, and light chains. The present disclosure also provides method of making the antibody or fragment thereof and methods of their use, including, in activating beta-klotho/FGF receptor complex, inducing FGF19-like and/or FGF21-like signaling, improving glucose and lipid metabolism, and treatment of nonalcoholic steatohepatitis.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: June 6, 2023
    Assignee: NGM Biopharmaceuticals, Inc.
    Inventors: Kalyani Mondal, Betty Chan Li, Yu Chen, Taruna Arora, Hugo Matern, Wenyan Shen
  • Patent number: 11652124
    Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Wei Huang, Chao-Ching Chang, Yun-Wei Cheng, Chih-Lung Cheng, Yen-Chang Chen, Wen-Jen Tsai, Cheng Han Lin, Yu-Hsun Chih, Sheng-Chan Li, Sheng-Chau Chen
  • Patent number: 11610812
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Publication number: 20230085313
    Abstract: An endodontic robotic surgical system is provided. The endodontic robotic surgical system includes a robot arm and an endodontic robotic surgical assembly electrically connected to the robot arm. The endodontic robotic surgical assembly includes a multiple-axis force sensing device, a treatment assembly and an assistive device. The treatment assembly includes a housing, a drawstring-positioning structure disposed on the housing, a plurality of drawstrings connected to the drawstring-positioning structure, and an endodontic surgical element fitted to the housing. The drawstring-positioning structure is electrically connected to the multiple-axis force sensing device. The assistive device is adapted to be put on a tooth structure in a human oral cavity. The drawstrings are connected to different points on the assistive device. An endodontic robotic surgical assembly is further provided.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Inventors: CHENG-WEI CHEN, YI-CHAN LI, HAO-FANG CHENG