Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

Abstract: An apparatus includes a beam conditioning assembly configured to output one or more wavelengths to a substrate being processed and receive one or more reflected wavelengths from the substrate, and a machine learning device configured to process the one or more reflected wavelengths to predict a process variable and compare the predicted process variable with a measured process variable to obtain a comparison result.

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

Abstract: A method for real-time compensation control of an etch process includes: providing a substrate having a layer in a process chamber; performing the etch process on the layer; directing one or more wavelengths to a region of the layer by a beam conditioning assembly; receiving one or more reflected wavelengths from the region of the layer; predicting a process variable by processing the one or more reflected wavelengths using a machine learning model; and comparing the predicted process variable with a predetermined process variable to obtain a comparison result.

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

Abstract: A fin field effect transistor (Fin FET) device includes fin structure extending in first direction and protruding from isolation insulating layer disposed over substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a stack of nanostructured channel regions disposed on a fin structure, a first gate structure disposed within the stack of nanostructured channel regions, a second gate structure surrounds the first gate structure about a first axis and surrounds the nanostructured channel regions about a second axis different from the first axis, and first and second contact structures disposed on the first and second gate structures, respectively.

Abstract: A method for generating an extreme ultraviolet (EUV) radiation includes simultaneously irradiating two or more target droplets with laser light in an EUV radiation source apparatus to produce EUV radiation and collecting and directing the EUV radiation produced from the two or more target droplet by an imaging mirror.

Abstract: The present disclosure relates to an ion beam etching (IBE) system including a plasma chamber configured to provide plasma, a screen grid, an extraction grid, an accelerator grid, and a decelerator grid. The screen grid receives a screen grid voltage to extract ions from the plasma within the plasma chamber to form an ion beam through a hole. The extraction grid receives an extraction grid voltage, where a voltage difference between the screen grid voltage and the extraction grid voltage determines an ion current density of the ion beam. The accelerator grid receives an accelerator grid voltage. A voltage difference between the extraction grid voltage and the accelerator grid voltage determines an ion beam energy for the ion beam. The IBE system can further includes a deflector system having a first deflector plate and a second deflector plate around a hole to control the direction of the ion beam.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a stack of nanostructured channel regions disposed on a fin structure, a first gate structure disposed within the stack of nanostructured channel regions, a second gate structure surrounds the first gate structure about a first axis and surrounds the nanostructured channel regions about a second axis different from the first axis, and first and second contact structures disposed on the first and second gate structures, respectively.

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

Abstract: The present disclosure relates to an ion beam etching (IBE) system including a plasma chamber configured to provide plasma, a screen grid, an extraction grid, an accelerator grid, and a decelerator grid. The screen grid receives a screen grid voltage to extract ions from the plasma within the plasma chamber to form an ion beam through a hole. The extraction grid receives an extraction grid voltage, where a voltage difference between the screen grid voltage and the extraction grid voltage determines an ion current density of the ion beam. The accelerator grid receives an accelerator grid voltage. A voltage difference between the extraction grid voltage and the accelerator grid voltage determines an ion beam energy for the ion beam. The IBE system can further includes a deflector system having a first deflector plate and a second deflector plate around a hole to control the direction of the ion beam.

Abstract: A method for generating an extreme ultraviolet (EUV) radiation includes simultaneously irradiating two or more target droplets with laser light in an EUV radiation source apparatus to produce EUV radiation and collecting and directing the EUV radiation produced from the two or more target droplet by an imaging mirror.

Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.