Patents by Inventor Chan-Lon Yang
Chan-Lon Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220037163Abstract: The present disclosure describes methods and systems for plasma-assisted etching of a metal oxide. The method includes modifying a surface of the metal oxide with a first gas, removing a top portion of the metal oxide by a ligand exchange reaction, and cleaning the surface of the metal oxide with a second gas.Type: ApplicationFiled: July 31, 2020Publication date: February 3, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David YANG, Keh-Jeng Chang, Chan-Lon Yang
-
Publication number: 20220013652Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.Type: ApplicationFiled: July 10, 2020Publication date: January 13, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David Yang, Chan-Lon Yang, Keh-Jeng Chang
-
Publication number: 20210384323Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David YANG, Keh-Jeng CHANG, Chan-Lon YANG
-
Publication number: 20210376137Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David YANG, Keh-Jeng Chang, Chan-Lon Yang
-
Patent number: 11150559Abstract: A method for generating an extreme ultraviolet (EUV) radiation includes simultaneously irradiating two or more target droplets with laser light in an EUV radiation source apparatus to produce EUV radiation and collecting and directing the EUV radiation produced from the two or more target droplet by an imaging mirror.Type: GrantFiled: July 27, 2020Date of Patent: October 19, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang
-
Publication number: 20210305409Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.Type: ApplicationFiled: May 28, 2021Publication date: September 30, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zhi-Qiang WU, Kuo-An LIU, Chan-Lon YANG, Bharath Kumar PULICHERLA, Li-Te LIN, Chung-Cheng WU, Gwan-Sin CHANG, Pinyen LIN
-
Patent number: 11114547Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.Type: GrantFiled: September 17, 2019Date of Patent: September 7, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang
-
Patent number: 11075282Abstract: A method includes forming a gate layer over a semiconductor fin; forming a patterned mask over the gate layer; performing a first etching process to pattern the gate layer using the patterned mask as an etch mask, the patterned gate layer comprising a first gate extending across the semiconductor fin; depositing, by using an directional ion beam, a protection layer to wrap around a top surface, a first sidewall and a second sidewall of the first gate, the protection layer extending along the first and second sidewalls of the first gate towards a bottom surface of the first gate without extending to the bottom surface of the first gate on the second sidewall of the first gate; and after depositing the protection layer, performing a second etching process to a portion of the second sidewall of the first gate exposed by the protection layer.Type: GrantFiled: November 19, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-An Liu, Chan-Lon Yang, Bharath Kumar Pulicherla, Zhi-Qiang Wu, Chung-Cheng Wu, Chih-Han Lin, Gwan-Sin Chang
-
Publication number: 20210200102Abstract: A method for generating an extreme ultraviolet (EUV) radiation includes simultaneously irradiating two or more target droplets with laser light in an EUV radiation source apparatus to produce EUV radiation and collecting and directing the EUV radiation produced from the two or more target droplet by an imaging mirror.Type: ApplicationFiled: July 27, 2020Publication date: July 1, 2021Inventors: Chansyun David YANG, Keh-Jeng CHANG, Chan-Lon YANG
-
Patent number: 11024721Abstract: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.Type: GrantFiled: September 3, 2019Date of Patent: June 1, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zhi-Qiang Wu, Kuo-An Liu, Chan-Lon Yang, Bharath Kumar Pulicherla, Li-Te Lin, Chung-Cheng Wu, Gwan-Sin Chang, Pinyen Lin
-
Publication number: 20210083074Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David YANG, Keh-Jeng CHANG, Chan-Lon YANG
-
Publication number: 20210050451Abstract: A method includes forming an implanted region in a substrate. The implanted region is adjacent to a top surface of the substrate. A clean treatment is performed on the top surface of the implanted region. The top surface of the implanted region is baked after the clean treatment. An epitaxial layer is formed on the top surface of the substrate. The epitaxial layer is patterned to form a fin.Type: ApplicationFiled: October 19, 2020Publication date: February 18, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Che-Yu LIN, Ming-Hua YU, Tze-Liang LEE, Chan-Lon YANG
-
Publication number: 20210036154Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.Type: ApplicationFiled: August 17, 2020Publication date: February 4, 2021Inventors: Kun-Mu LI, Tsz-Mei KWOK, Ming-Hua YU, Chan-Lon YANG
-
Patent number: 10868139Abstract: A method includes forming a dummy gate electrode layer over a semiconductor region, forming a mask strip over the dummy gate electrode layer, and performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer. A remaining portion of the upper portion of the dummy gate electrode layer forms an upper part of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper part of the dummy gate electrode, and performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, with the protection layer and the mask strip in combination used as a second etching mask. The dummy gate electrode and an underlying dummy gate dielectric are replaced with a replacement gate stack.Type: GrantFiled: September 13, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Han Lin, Kuei-Yu Kao, Ming-Ching Chang, Chan-Lon Yang, Chao-Cheng Chen, Syun-Ming Jang
-
Patent number: 10811537Abstract: A device includes a semiconductor substrate, an isolation structure, and an epitaxial fin portion. The semiconductor substrate has an implanted region. The implanted region has a bottom fin portion thereon, in which a depth of the implanted region is smaller than a thickness of the semiconductor substrate. The isolation structure surrounds the bottom fin portion. The epitaxial fin portion is disposed over a top surface of the bottom fin portion, in which the implanted region of the semiconductor substrate includes oxygen and has an oxygen concentration lower than about 1·E+19 atoms/cm3.Type: GrantFiled: July 13, 2018Date of Patent: October 20, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Che-Yu Lin, Ming-Hua Yu, Tze-Liang Lee, Chan-Lon Yang
-
Publication number: 20200279920Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventors: Tetsuji UENO, Ming-Hua YU, Chan-Lon YANG
-
Patent number: 10749029Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.Type: GrantFiled: December 19, 2018Date of Patent: August 18, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kun-Mu Li, Tsz-Mei Kwok, Ming-Hua Yu, Chan-Lon Yang
-
Patent number: 10658491Abstract: A method includes forming a dummy gate electrode layer over a semiconductor region, forming a mask strip over the dummy gate electrode layer, and performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer. A remaining portion of the upper portion of the dummy gate electrode layer forms an upper part of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper part of the dummy gate electrode, and performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, with the protection layer and the mask strip in combination used as a second etching mask. The dummy gate electrode and an underlying dummy gate dielectric are replaced with a replacement gate stack.Type: GrantFiled: June 15, 2018Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Han Lin, Kuei-Yu Kao, Ming-Ching Chang, Chan-Lon Yang, Chao-Cheng Chen, Syun-Ming Jang
-
Patent number: 10658468Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.Type: GrantFiled: November 30, 2018Date of Patent: May 19, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang
-
Publication number: 20200111893Abstract: A method includes forming a gate layer over a semiconductor fin; forming a patterned mask over the gate layer; performing a first etching process to pattern the gate layer using the patterned mask as an etch mask, the patterned gate layer comprising a first gate extending across the semiconductor fin; depositing, by using an directional ion beam, a protection layer to wrap around a top surface, a first sidewall and a second sidewall of the first gate, the protection layer extending along the first and second sidewalls of the first gate towards a bottom surface of the first gate without extending to the bottom surface of the first gate on the second sidewall of the first gate; and after depositing the protection layer, performing a second etching process to a portion of the second sidewall of the first gate exposed by the protection layer.Type: ApplicationFiled: November 19, 2019Publication date: April 9, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-An LIU, Chan-Lon YANG, Bharath Kumar PULICHERLA, Zhi-Qiang WU, Chung-Cheng WU, Chih-Han LIN, Gwan-Sin CHANG