Patents by Inventor Chan-Lon Yang

Chan-Lon Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150380512
    Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.
    Type: Application
    Filed: September 9, 2015
    Publication date: December 31, 2015
    Inventors: Chan-Lon Yang, Chi-Mao Hsu, Chun-Yuan Wu, Tzyy-Ming Cheng, Shih-Fang Tzou, Chin-Fu Lin, Hsin-Fu Huang, Min-Chuan Tsai
  • Metal gate structure and manufacturing method thereof
    Patent number: 9166020
    Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: October 20, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chan-Lon Yang, Chi-Mao Hsu, Chun-Yuan Wu, Tzyy-Ming Cheng, Shih-Fang Tzou, Chin-Fu Lin, Hsin-Fu Huang, Min-Chuan Tsai
  • SEMICONDUCTOR PROCESS
    Publication number: 20150104914
    Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is cryo-implanted with at least two of multiple species including a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between ?40° C. and ?120° C. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.
    Type: Application
    Filed: November 24, 2014
    Publication date: April 16, 2015
    Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li
  • Semiconductor device having metal gate and manufacturing method thereof
    Patent number: 8999830
    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 7, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
  • Metal gate transistor and method for fabricating the same
    Patent number: 8980753
    Abstract: A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: March 17, 2015
    Assignee: United Mircroelectronics Corp.
    Inventors: Yeng-Peng Wang, Chun-Hsien Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chan-Lon Yang
  • Semiconductor device having metal gate and manufacturing method thereof
    Patent number: 8952451
    Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
  • POLYSILICON LAYER
    Publication number: 20150021776
    Abstract: A polysilicon layer including an amorphous polysilicon layer and a crystallized polysilicon layer is provided. The crystallized polysilicon layer is disposed on the amorphous polysilicon layer. Besides, the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size. The amorphous polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the crystallized polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • Semiconductor process
    Patent number: 8921206
    Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Ching-I Li, Ger-Pin Lin, I-Ming Lai, Yun-San Huang, Chin-I Liao, Chin-Cheng Chien
  • Polysilicon layer and method of forming the same
    Patent number: 8895435
    Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Yun-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • Strained silicon channel semiconductor structure
    Patent number: 8853740
    Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: October 7, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Ted Ming-Lang Guo, Chin-I Liao, Chin-Cheng Chien, Shu-Yen Chan, Chun-Yuan Wu
  • Method of manufacturing semiconductor device having metal gates
    Patent number: 8802524
    Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yi-Wei Chen, Hsin-Fu Huang, Tzung-Ying Lee, Min-Chuan Tsai, Chan-Lon Yang, Chun-Yuan Wu, Teng-Chun Tsai, Guang-Yaw Hwang, Chia-Lin Hsu, Jie-Ning Yang, Cheng-Guo Chen, Jung-Tsung Tseng, Zhi-Cheng Lee, Hung-Ling Shih, Po-Cheng Huang, Yi-Wen Chen, Che-Hua Hsu
  • Semiconductor process
    Patent number: 8765588
    Abstract: A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: July 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Pong-Wey Huang, Chan-Lon Yang, Chang-Hung Kung, Wei-Hsin Liu, Ya-Hsueh Hsieh, Bor-Shyang Liao, Teng-Chun Hsuan, Chun-Yao Yang
  • SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF
    Publication number: 20140127892
    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
    Type: Application
    Filed: December 19, 2013
    Publication date: May 8, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
  • Semiconductor device having metal gate and manufacturing method thereof
    Patent number: 8704294
    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: April 22, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
  • SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF
    Publication number: 20140103443
    Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 17, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
  • SEMICONDUCTOR PROCESS
    Publication number: 20130337622
    Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.
    Type: Application
    Filed: August 20, 2013
    Publication date: December 19, 2013
    Applicant: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li
  • Method of manufacturing semiconductor device having metal gate
    Patent number: 8574990
    Abstract: The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: November 5, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Shui-Yen Lu, Pei-Yu Chou, Shin-Chi Chen, Jiunn-Hsiung Liao, Shang-Yuan Tsai, Chan-Lon Yang, Teng-Chun Tsai, Chun-Hsien Lin
  • Semiconductor device and manufacturing method thereof
    Patent number: 8575043
    Abstract: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an included angle.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 5, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Tzu-Feng Kuo, Hsin-Huei Wu, Ching-I Li, Shu-Yen Chan
  • STRAINED SILICON CHANNEL SEMICONDUCTOR STRUCTURE
    Publication number: 20130256701
    Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.
    Type: Application
    Filed: May 30, 2013
    Publication date: October 3, 2013
    Inventors: Chan-Lon Yang, Ted Ming-Lang Guo, Chin-I Liao, Chin-Cheng Chien, Shu-Yen Chan, Chun-Yuan Wu
  • Semiconductor process
    Patent number: 8536072
    Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: September 17, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li