Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract: A method for improving a call-participant behavior, the method includes receiving an intensity data signal and an intensity variation data signal related to an ongoing call, receiving a pitch data signal and a pitch variation data signal related to the ongoing call, receiving a tempo data signal and a tempo variation data signal related to the ongoing call, receiving a channel comparison data signal related to the ongoing call, generating a real-time call progress signal based on the intensity data signal, the intensity variation data signal, the pitch data signal, the pitch variation data signal, the tempo data signal, the tempo variation data signal, and the channel comparison data signal, and sending the real-time call progress signal to a user device.

Abstract: A memory includes a first memory cell and a second memory cell formed over the first memory cell. Each of the first memory cell and the second memory cell includes a channel region comprising silicon and carbon, a control gate, and a dielectric stack between the channel region and the control gate. A carbon content of the channel region of the second memory cell is less than a carbon content of the channel region of the first memory cell.

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

Abstract: A method for altering bandwidth consumption when receiving content in a user device includes determining a first user device status where the first user device status indicates whether content, which is being accessed by a content-rendering application, is viewable on a display of the user device, based on the first user device status, selecting one of a plurality of available alternative content segments, and receiving the selected content segment.

Abstract: Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor material capable of electronic switching and having a first band gap is between the first and second electrodes. A material is in contact with the semiconductor material and having a second band gap, the second band gap greater than the first band gap.

Abstract: Devices for providing transistors with improved operating characteristics are provided. In one example, a system includes a processor and a memory device. A transistor of the processor or the memory device includes a channel in a semiconductor substrate that is undoped or intrinsic. A metal gate is disposed directly on top of the channel, and the bandgap of the semiconductor substrate and the work function of the metal form a Schottky barrier.

Abstract: A video encoder may reduce bandwidth consumption by skipping encoding of or reducing an encoding rate of video frames corresponding to silent audio frames, that is, audio frames that do not include speech data. In one example, an apparatus includes a video encoder comprising a coding unit configured to encode video data in a first or second mode and a mode select unit configured to receive an indication of whether encoded audio data corresponding to the video data to be encoded includes speech data. When the audio data includes speech data, the mode select unit selects the first mode, and when the audio data does not include speech data, the mode select unit selects the second mode. The second mode consumes relatively less bandwidth, e.g., by reducing a bitrate, modifying a quantization parameter to increase quantization, and/or reducing a frame rate relative to the first mode.

Abstract: The present disclosure describes methods and systems for managing resources, for example in connection with call admission control or other communications or transactions in a system. In particular, a plurality of resource pools are established. At least a first or priority resource is associated with a minimum resource amount, while at least a second or normal resource pool is associated with a maximum resource amount. From the system resource pools, allocations are made to each of a plurality of system servers. If a server receives a request for priority resources that cannot be satisfied from the allocation of priority resources made to that server, that server may borrow from an allocation of normal resources. Resources can also be shared between servers. Accordingly, if required resources are not available from an allocation made to a server receiving the request for resources, that server can request resources from another server.

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

Abstract: This disclosure provides systems, methods and apparatus for wirelessly communicating with a wireless station. In one implementation, a mobile device comprises a memory unit configured to store communication information associated with communicating on at least one channel of a wireless network. The mobile device further comprises a processing system that is configured to establish communications with the wireless station via a communication link, retrieve the communication information from the memory unit, and to provide at least a portion of the communication information to the wireless station.

Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.

Abstract: Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods may be used in the channel region of an access transistor. The nanorod diameter can be made small enough to cause an increase in the electronic band gap energy in the channel region of the access transistor, which may serve to limit channel leakage currents in its off-state. In various embodiments, the access transistor may be electrically coupled to a double-sided capacitor. Memory devices according to embodiments of the invention, and systems including such devices are also disclosed.

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

Abstract: A distributed call control system is provided that can allot bandwidth amongst several call controllers. The distributed call control system includes one or more access elements that interface with a cloud that execute two or more instances of call processing servers that administer call control. The cloud members negotiate and determine bandwidth allocation amongst the members and the access elements. If an access element requires more bandwidth, the access element assesses its own needs and requests more bandwidth from the cloud. The negotiation and requests for bandwidth are accomplished with a set of dynamic and static bandwidth data that regiment the control of the bandwidth.

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.