Patents by Inventor Chandra Mouli

Chandra Mouli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing devices having vertical junction edge
    Patent number: 8501602
    Abstract: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: August 6, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Chandra Mouli
  • Semiconductor constructions comprising vertically-stacked memory units that include diodes utilizing at least two different dielectric materials, and electronic systems
    Patent number: 8487450
    Abstract: Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: July 16, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • JFET device structures and methods for fabricating the same
    Patent number: 8481372
    Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • SIP TRANSFER IN A BACK-TO-BACK USER AGENT (B2BUA) ENVIRONMENT
    Publication number: 20130173812
    Abstract: The system generates a change in the SIP INVITE message during a call transfer. Here, a user relation element involved in the call can change the header information in the message to include the endpoint view of the transferring party. Thus, the INVITE message is redirected to the transferring party's user relation element, which can interpret the received message and “unravel” the B2BUAs in the existing call path. The system includes changes in the user relation element to effect the message change and interpret the message once received. Changes to the user relation element forgo the need to change the communication endpoints.
    Type: Application
    Filed: May 31, 2012
    Publication date: July 4, 2013
    Applicant: AVAYA INC.
    Inventors: Joel Ezell, Gordon R. Brunson, Chandra Mouli Ravipati, Harsh V. Mendiratta
  • Methods of making random access memory devices, transistors, and memory cells
    Patent number: 8470666
    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: June 25, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Recessed Channel Negative Differential Resistance-Based Memory Cell
    Publication number: 20130140601
    Abstract: The disclosed recessed thyristor-based memory cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode is connected to the bit line and cathode is connected to the word line. The disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device. As facilitated by the vertical disposition of the thyristor, the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell. The disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells. Isolation underneath the cell assists in improving the data retention of the cell and extends the time needed between cell refresh.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 6, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Chandra Mouli
  • SEMICONDUTOR ISOLATION STRUCTURE AND METHOD OF MANUFACTURE
    Publication number: 20130140631
    Abstract: A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventors: Kamal Karda, Chandra Mouli
  • High density thyristor random access memory device and method
    Patent number: 8455919
    Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: June 4, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Suraj J. Mathew, Chandra Mouli
  • Communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses
    Patent number: 8447147
    Abstract: Some embodiments include communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses. In one embodiment, a communication method includes accessing an optical signal comprising photons to communicate information, accessing an electrical signal comprising electrical data carriers to communicate information, and using a single interconnect, communicating the optical and electrical signals between a first spatial location and a second spatial location spaced from the first spatial location.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: May 21, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Memory devices with a connecting region having a band gap lower than a band gap of a body region
    Patent number: 8431961
    Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: April 30, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Jian Li, Chandra Mouli
  • Memory devices and memory cells
    Patent number: 8415722
    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 9, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Method for fabricating stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors
    Patent number: 8404536
    Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Floating body field-effect transistors, and methods of forming floating body field-effect transistors
    Patent number: 8395214
    Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: March 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Di Li, Michael P. Violette, Chandra Mouli, Howard Kirsch
  • EFFICIENT AND COST-EFFECTIVE DISTRIBUTED CALL ADMISSION CONTROL
    Publication number: 20130022192
    Abstract: A distributed call control system is provided that can allot bandwidth amongst several call controllers. The distributed call control system includes one or more access elements that interface with a cloud that execute two or more instances of call processing servers that administer call control. The cloud members negotiate and determine bandwidth allocation amongst the members and the access elements. If an access element requires more bandwidth, the access element assesses its own needs and requests more bandwidth from the cloud. The negotiation and requests for bandwidth are accomplished with a set of dynamic and static bandwidth data that regiment the control of the bandwidth.
    Type: Application
    Filed: July 21, 2011
    Publication date: January 24, 2013
    Applicant: AVAYA INC.
    Inventors: James Douglas Free, Christopher D. Baldwin, Chandra Mouli Ravipati, Gordon R. Brunson
  • Methods of forming memory cells
    Patent number: 8357967
    Abstract: Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: January 22, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • HIGH DENSITY THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD
    Publication number: 20130009208
    Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.
    Type: Application
    Filed: September 15, 2012
    Publication date: January 10, 2013
    Inventors: Suraj J Mathew, Chandra Mouli
  • Methods of Forming Diodes
    Publication number: 20120329210
    Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.
    Type: Application
    Filed: August 30, 2012
    Publication date: December 27, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej S. Sandhu, Chandra Mouli
  • LOW POWER MEMORY DEVICE WITH JFET DEVICE STRUCTURES
    Publication number: 20120329226
    Abstract: There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation.
    Type: Application
    Filed: September 5, 2012
    Publication date: December 27, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • METHODS OF MAKING JFET DEVICES WITH PIN GATE STACKS
    Publication number: 20120302015
    Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.
    Type: Application
    Filed: July 30, 2012
    Publication date: November 29, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Method and apparatus providing an optical guide in image sensor devices
    Patent number: 8304707
    Abstract: A device and method for providing an optical guide of a pixel to guide incoming light to/from a photo-conversion device of the pixel to improve the optical crosstalk immunity. The optical guide includes an optically reflecting barrier formed as a trench filled with a material which produces reflection. The trench fill material may have an index of refraction that is less than the index of refraction of the material used for the trench surrounding layers to provide a light reflective structure or the trench fill material may provide a reflection surface.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: November 6, 2012
    Assignee: Aptina Imaging Corporation
    Inventors: Ji Soo Lee, Jeff A. Mckee, Chandra Mouli