Patents by Inventor Chandrasekharan Kothandaraman

Chandrasekharan Kothandaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12063867
    Abstract: An approach to provide a structure of a double magnetic tunnel junction device with two spacers that includes a bottom magnetic tunnel junction stack, a spin conducting layer on the bottom magnetic tunnel junction stack, a top magnetic tunnel junction stack on the spin conduction layer, a first dielectric spacer on sides of the top magnetic tunnel junction stack and a portion of a top surface of the spin conduction layer, and a second dielectric spacer on the first spacer. The double magnetic tunnel device includes the top magnetic tunnel junction stack with a width that is less than the width of the bottom magnetic tunnel junction stack.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: August 13, 2024
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Chandrasekharan Kothandaraman, Nathan P. Marchack
  • Patent number: 11980039
    Abstract: A semiconductor device including a second magnetic tunnel junction stack aligned above a spin conductor layer above a first magnetic junction stack, a sidewall dielectric surrounding the second magnetic tunnel junction stack, a vertical side surface of the sidewall dielectric is aligned with vertical side surfaces of the spin conductor layer and the first magnetic junction stack. A method including forming a first magnetic tunnel junction stack, a spin conductor layer and a second magnetic tunnel junction stack, patterning the second magnetic tunnel junction stack, while not patterning the spin conductor layer and the first magnetic tunnel junction stack, forming a sidewall dielectric and a polymer layer on the sidewall dielectric. A method including patterning a second magnetic tunnel junction stack, while not patterning a spin conductor layer below the second magnetic tunnel junction stack nor a first magnetic tunnel junction stack below the spin conductor layer.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: May 7, 2024
    Assignee: International Business Machines Corporation
    Inventors: Nathan P. Marchack, Chandrasekharan Kothandaraman, Pouya Hashemi
  • Publication number: 20240145515
    Abstract: An integrated circuit package (34, 34?, 34?) may be implemented by stacked first, second, and third integrated circuit dies (40, 50, 60). The first and second dies (40, 50) may be bonded to each other using corresponding inter-die connection structures (74-1, 84-1) at respective interfacial surfaces facing the other die. The second die (50) may also include a metal layer (84-2) for connecting to the third die (60) at its interfacial surface with the first die (40). The metal layer (84-2) may be connected to a corresponding inter-die connection structure (64) on the side of the third die (60) facing the second die (50) through a conductive through-substrate via (84-2) and an additional metal layer (102) in a redistribution layer (96) between the second and third dies (50, 60). The third die (60) may have a different lateral outline than the second die (50).
    Type: Application
    Filed: April 27, 2022
    Publication date: May 2, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swarnal BORTHAKUR, Mario M. PELELLA, Chandrasekharan KOTHANDARAMAN, Marc Allen SULFRIDGE, Yusheng LIN, Larry Duane KINSMAN
  • Patent number: 11937512
    Abstract: A semiconductor device including a magnetic tunnel junction stack, a metallic hard mask aligned above the magnetic tunnel junction stack and an air gap surrounding the metallic hard mask. A method including forming a magnetic tunnel junction stack, forming a metallic hard mask aligned above the magnetic tunnel junction stack, conformally forming a dielectric over the metallic hard mask and the magnetic tunnel junction stack, forming barrier on vertical side surfaces of the dielectric, and removing the dielectric between the metallic hard mask and the barrier. A method including forming a magnetic tunnel junction stack, forming a metallic hard mask aligned above the magnetic tunnel junction stack, conformally forming a dielectric over the metallic hard mask and the magnetic tunnel junction stack, selectively removing a portion of the dielectric surrounding the metallic hard mark.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: March 19, 2024
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Nathan P. Marchack, Pouya Hashemi
  • Patent number: 11844284
    Abstract: A method of manufacturing and resultant device are directed to an inverted wide-base double magnetic tunnel junction device having both high-efficiency and high-retention arrays. The method includes a method of manufacturing, on a common stack, a high-efficiency array and a high-retention array for an inverted wide-base double magnetic tunnel junction device. The method comprises, for the high-efficiency array and the high-retention array, forming a first magnetic tunnel junction stack (MTJ2), forming a spin conducting layer on the MTJ2, and forming a second magnetic tunnel junction stack (MTJ1) on the spin conducting layer. The first magnetic tunnel junction stack for the high-retention array has a high-retention critical dimension (CD) (HRCD) that is larger than a high-efficiency CD (HECD) of the first magnetic tunnel junction stack for the high-efficiency array. The second magnetic tunnel junction stack (MTJ1) is shorted for the high-retention array and is not shorted for the high-efficiency array.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 12, 2023
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Chandrasekharan Kothandaraman
  • Patent number: 11778921
    Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack, forming a spin conducting layer on the first magnetic tunnel junction stack, forming a second magnetic tunnel junction stack on the spin conducting layer, and forming a dielectric spacer layer on surfaces of the spin conducting layer and the second magnetic tunnel junction stack. The second magnetic tunnel junction stack has a width that is less than a width of the first magnetic tunnel junction stack. Also, a width of the spin conducting layer increases in a thickness direction from a first side of the spin conducting layer adjacent to the second magnetic tunnel junction stack to a second side of the spin conducting layer adjacent to the first magnetic tunnel junction stack.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: October 3, 2023
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Bruce B. Doris, Chandrasekharan Kothandaraman, Jonathan Zanhong Sun
  • Publication number: 20230039834
    Abstract: An approach to provide a structure of a double magnetic tunnel junction device with two spacers that includes a bottom magnetic tunnel junction stack, a spin conducting layer on the bottom magnetic tunnel junction stack, a top magnetic tunnel junction stack on the spin conduction layer, a first dielectric spacer on sides of the top magnetic tunnel junction stack and a portion of a top surface of the spin conduction layer, and a second dielectric spacer on the first spacer. The double magnetic tunnel device includes the top magnetic tunnel junction stack with a width that is less than the width of the bottom magnetic tunnel junction stack.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 9, 2023
    Inventors: Pouya Hashemi, Chandrasekharan KOTHANDARAMAN, NATHAN P. MARCHACK
  • Patent number: 11563054
    Abstract: A memory element and methods of constructing the memory element are described. The memory element may include a bottom electrode structure having an uppermost portion of a first dimension. The memory element may further include a MTJ pillar having a bottommost portion forming an interface with the uppermost portion of the bottom electrode structure. The bottommost portion of the MTJ pillar may have a second dimension that is less than the first dimension. The memory element may further include oxidized metal particles located on an outermost sidewall of the MTJ pillar. The memory element may further include a top electrode structure located in the MTJ pillar.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Dimitri Houssameddine, Chandrasekharan Kothandaraman, Bruce B. Doris
  • Publication number: 20220416156
    Abstract: A method of manufacturing and resultant device are directed to an inverted wide-base double magnetic tunnel junction device having both high-efficiency and high-retention arrays. The method includes a method of manufacturing, on a common stack, a high-efficiency array and a high-retention array for an inverted wide-base double magnetic tunnel junction device. The method comprises, for the high-efficiency array and the high-retention array, forming a first magnetic tunnel junction stack (MTJ2), forming a spin conducting layer on the MTJ2, and forming a second magnetic tunnel junction stack (MTJ1) on the spin conducting layer. The first magnetic tunnel junction stack for the high-retention array has a high-retention critical dimension (CD) (HRCD) that is larger than a high-efficiency CD (HECD) of the first magnetic tunnel junction stack for the high-efficiency array. The second magnetic tunnel junction stack (MTJ1) is shorted for the high-retention array and is not shorted for the high-efficiency array.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 29, 2022
    Inventors: Pouya Hashemi, Chandrasekharan KOTHANDARAMAN
  • Publication number: 20220406841
    Abstract: A semiconductor device including a second magnetic tunnel junction stack aligned above a spin conductor layer above a first magnetic junction stack, a sidewall dielectric surrounding the second magnetic tunnel junction stack, a vertical side surface of the sidewall dielectric is aligned with vertical side surfaces of the spin conductor layer and the first magnetic junction stack. A method including forming a first magnetic tunnel junction stack, a spin conductor layer and a second magnetic tunnel junction stack, patterning the second magnetic tunnel junction stack, while not patterning the spin conductor layer and the first magnetic tunnel junction stack, forming a sidewall dielectric and a polymer layer on the sidewall dielectric. A method including patterning a second magnetic tunnel junction stack, while not patterning a spin conductor layer below the second magnetic tunnel junction stack nor a first magnetic tunnel junction stack below the spin conductor layer.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 22, 2022
    Inventors: NATHAN P. MARCHACK, Chandrasekharan KOTHANDARAMAN, Pouya Hashemi
  • Publication number: 20220393102
    Abstract: A semiconductor device including a magnetic tunnel junction stack, a metallic hard mask aligned above the magnetic tunnel junction stack and an air gap surrounding the metallic hard mask. A method including forming a magnetic tunnel junction stack, forming a metallic hard mask aligned above the magnetic tunnel junction stack, conformally forming a dielectric over the metallic hard mask and the magnetic tunnel junction stack, forming barrier on vertical side surfaces of the dielectric, and removing the dielectric between the metallic hard mask and the barrier. A method including forming a magnetic tunnel junction stack, forming a metallic hard mask aligned above the magnetic tunnel junction stack, conformally forming a dielectric over the metallic hard mask and the magnetic tunnel junction stack, selectively removing a portion of the dielectric surrounding the metallic hard mark.
    Type: Application
    Filed: June 2, 2021
    Publication date: December 8, 2022
    Inventors: Chandrasekharan KOTHANDARAMAN, NATHAN P. MARCHACK, Pouya Hashemi
  • Patent number: 11487508
    Abstract: A true random number generator (TRNG) device having a magnetic tunnel junction (MTJ) structure coupled to a domain wall wire. The MTJ structure is formed of a free layer (FL) and a reference layer (RL) that sandwiches a tunnel barrier layer. The free layer has anisotropy energy sufficiently low to provide stochastic fluctuation in the orientation of the magnetic state of the free layer via thermal energy. The domain wall wire is coupled to the MTJ structure. The domain wall wire has a domain wall. Movement of the domain wall tunes a probability distribution of the fluctuation in the orientation of the magnetic state of the free layer. The domain wall can be moved by application of a suitable current through the wire to tune the probability distribution of 1's and 0's generated by a readout circuit of the TRNG device.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: November 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Rasit O. Topaloglu, Jonathan Z. Sun, Matthias G. Gottwald, Chandrasekharan Kothandaraman
  • Publication number: 20220199898
    Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack, forming a spin conducting layer on the first magnetic tunnel junction stack, forming a second magnetic tunnel junction stack on the spin conducting layer, and forming a dielectric spacer layer on surfaces of the spin conducting layer and the second magnetic tunnel junction stack. The second magnetic tunnel junction stack has a width that is less than a width of the first magnetic tunnel junction stack. Also, a width of the spin conducting layer increases in a thickness direction from a first side of the spin conducting layer adjacent to the second magnetic tunnel junction stack to a second side of the spin conducting layer adjacent to the first magnetic tunnel junction stack.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Pouya Hashemi, Bruce B. Doris, Chandrasekharan KOTHANDARAMAN, Jonathan Zanhong Sun
  • Patent number: 11226252
    Abstract: A sub-micrometer pressure sensor is provided that includes a multilayered magnetic tunnel junction (MTJ) pillar that contains a non-magnetic metallic spacer separating a first magnetic free layer from a second magnetic free layer. The presence of the non-magnetic metallic spacer in the multilayered MTJ pillar improves the sensitivity without compromising area, and makes the pressure sensor binary (either “on” or “off”) with little or no drift, and sensitivity change over time. Moreover, the resistivity switch in such a pressure sensor is instantly and a low error rate is observed.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: January 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Virat Vasav Mehta, Alexander Reznicek, Chandrasekharan Kothandaraman, Eric Raymond Evarts, Pouya Hashemi
  • Patent number: 11205015
    Abstract: A memory system in an integrated circuit and a method of operation. The system includes multiple magnetic tunnel junction (MTJ) structures, each MTJ structure storing a logic value according to a resistive state. A selection switch device associated with a respective MTJ structure is activated to select one of the multiple MTJ structures at a time. An output circuit is configured to sense the resistive state of a selected MTJ structure, the output circuit having a selectable input reference resistance value according to a selected first reference resistance or a second reference resistance value, and outputting a first logic value of the selected MTJ structure responsive to a resistive state of the MTJ structure and a selected first resistance reference value, or alternately outputting a second logic value of the selected MTJ structure responsive to the resistive state of the MTJ structure and a selected second resistance reference value.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Dimitri Houssameddine, Bruce B. Doris
  • Publication number: 20210151503
    Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The structure is a MRAM element having a first conductive electrode embedded in a first interconnect dielectric material layer upon which a multi-layered magnetic tunnel junction (MTJ) memory element is formed in a magnetoresistive random access memory (MRAM) device area. The first conductive electrode includes a first end having a top surface of a first surface area and a second end having a bottom surface of a second surface area, the first surface area being smaller than the second surface area. The second end of the bottom electrode includes a barrier liner material including a metal fill material, and the first end of the bottom electrode is a pillar structure formed as a result of an etchback process in which the metal barrier liner is recessed relative to the metal fill material.
    Type: Application
    Filed: December 29, 2020
    Publication date: May 20, 2021
    Inventors: Pouya Hashemi, Bruce B.` Doris, Chandrasekharan Kothandaraman, Nathan P. Marchack
  • Patent number: 10984948
    Abstract: A method for forming an inductor device. The method comprises forming a trench within a central core region of a conductive coil formed within a dielectric material. The method further comprises forming a composite region within the trench. The composite region including a polymer matrix having a plurality of particles with magnetic properties dispersed therein with the central core region to reduce eddy current loss and increase energy storage.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chandrasekharan Kothandaraman, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 10957738
    Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The structure is a MRAM element having a first conductive electrode embedded in a first interconnect dielectric material layer upon which a multi-layered magnetic tunnel junction (MTJ) memory element is formed in a magnetoresistive random access memory (MRAM) device area. The first conductive electrode includes a first end having a top surface of a first surface area and a second end having a bottom surface of a second surface area, the first surface area being smaller than the second surface area. The second end of the bottom electrode includes a barrier liner material including a metal fill material, and the first end of the bottom electrode is a pillar structure formed as a result of an etchback process in which the metal barrier liner is recessed relative to the metal fill material.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Bruce B. Doris, Chandrasekharan Kothandaraman, Nathan P. Marchack
  • Patent number: 10942072
    Abstract: A sub-micrometer pressure sensor including a multilayered magnetic tunnel junction (MTJ) pillar containing a magnetostrictive material layer above or below a magnetic free layer of the multilayered MTJ pillar is provided. Advanced patterning allows for scaling of the multilayered MTJ pillar down to 25 nm or below which enables the formation of a large array of extremely high resolution pressure sensors. By varying the thickness of the magnetostrictive material layer, the sensitivity of the pressure sensor can be fine tuned. Unique magnetostrictive materials in the multilayered MTJ pillar will alter the device current with the input of external pressure. Furthermore, unique arrays with much smaller critical elements can be organized in differential sensing arrangements of the multilayered MTJ pillar with pressure sensing capability that can outperform current piezoelectric based pressure sensing arrays.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Eric Raymond Evarts, Virat Vasav Mehta, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10937828
    Abstract: Fabricating a magnetoresistive random access memory (MRAM) device includes receiving a wafer structure having a first inter-layer dielectric (ILD) layer and a metal material disposed within the first ILD layer. A second ILD layer is deposited upon a top surface of the first ILD layer and the metal material. A trench is formed within the second ILD layer extending to the top surface of the metal material. A plurality of magnetic stack layers of a magnetic stack and an electrode layer are deposited within the trench. Portions of each of the magnetic stack layers of the magnetic stack and the electrode layer are removed to form a v-shaped magnetic tunnel junction (MTJ) in contact with the metal material.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pouya Hashemi, Matthias Georg Gottwald, Alexander Reznicek, Chandrasekharan Kothandaraman