Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junctions serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage, such that when the second field effect transistor of a selected magnetic tunnel junction is switched to direct the programming voltage to program the selected magnetic tunnel junction an unswitched magnetic tunnel junction and the second field effect transistor do not experience a voltage drop across the gates thereof sufficient to degrade.

Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate. At least one trench line is formed within the substrate. A pad layer is formed in contact with the at least one trench line. A seed layer is formed on and in contact with the pad layer. The seed layer has a Root Mean Square surface roughness equal to or less than 3 Angstroms. A magnetic tunnel junction stack is formed on and in contact with the seed layer. The method includes forming a seed layer on and in contact with a semiconductor structure. The seed layer is annealed and then planarized. A magnetic tunnel junction stack is formed on and in contact with the seed layer after the seed layer has been planarized.

Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.

Abstract: A method of fabricating a magneto-resistive random access memory (MRAM) cell with at least one magnetic tunnel junction (MTJ) is provided. The method includes disposing a metallic landing pad within a dielectric pad in a substrate and selectively depositing seed layer material over the substrate. This selective deposition forms a seed layer on which the MTJ is disposable on the metallic landing pad but not the dielectric pad.

Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer.

Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: An on-chip strain gage for monitoring strain on an integrated circuit (IC) chip, the IC chip and method of monitoring and mitigating stress induced chip warpage. The strain gage sensor includes a strain sensor element in a single layer. The strain gage sensor quantifies and digitizes local strain which reflects local chip stress from chip warpage. During normal chip usage, the strain information may be used to alter chip operation.

Abstract: Methods for forming magnetic tunnel junctions and structures thereof include cryogenic etching the layers defining the magnetic tunnel junction without lateral diffusion of reactive species.

Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.

Abstract: A method is presented for determining strain in a magnetoresistive random access memory (MRAM) structure. The method includes exposing long lines of the MRAM structure to monochromatic light to produce a diffraction pattern, measuring changes in interference fringe spacing in the diffraction pattern, determining the changes in the local strain in the MRAM structure from the measured changes in the interference fringe spacing, and assessing a performance of the MRAM structure from values of the changes in the local strain.

Abstract: A method is presented for determining strain in a magnetoresistive random access memory (MRAM) structure. The method includes exposing long lines of the MRAM structure to monochromatic light to produce a diffraction pattern, measuring changes in interference fringe spacing in the diffraction pattern, determining the changes in the local strain in the MRAM structure from the measured changes in the interference fringe spacing, and assessing a performance of the MRAM structure from values of the changes in the local strain.

Abstract: Methods for forming magnetic tunnel junctions and structures thereof include cryogenic etching the layers defining the magnetic tunnel junction without lateral diffusion of reactive species.

Abstract: A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.

Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: An apparatus, method, system, and program product are disclosed for intrinsic chip identification. One method includes receiving first counter information from a device, determining whether such information matches second counter information, receiving first frequencies from the device, determining whether each frequency of such frequencies is within a predetermined range of a corresponding frequency of second frequencies, receiving a response to a challenge sent to the device, determining whether the response matches an expected response, and granting authentication. Granting authentication may include granting authentication in response to: the first counter information matching the second counter information; each frequency of the first frequencies being within the predetermined range of a corresponding frequency of the second frequencies; and the expected response matching the response. The expected response may be updated over time.

Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: An apparatus is presented for generating a true random number generator (TRNG). The apparatus includes a magnetic tunnel junction (MTJ) device including a first layer, a second layer, and third layer, as well as a bias circuit to bias the MTJ device along with a pulse height discriminator and a time-to-amplitude convertor to generate random bit-streams. The second layer is a barrier layer with an energy barrier height in the order of 20 kT, where k is the Boltzmann constant and T is the absolute temperature. Random flipping of an orientation of magnetization of the third layer is induced by thermal fluctuations in the MTJ device.