Patents by Inventor Chandrasekharan Kothandaraman

Chandrasekharan Kothandaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SELECTIVE GROWTH OF SEED LAYER FOR MAGNETO-RESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20180261763
    Abstract: A method of fabricating a magneto-resistive random access memory (MRAM) cell with at least one magnetic tunnel junction (MTJ) is provided. The method includes disposing a metallic landing pad within a dielectric pad in a substrate and selectively depositing seed layer material over the substrate. This selective deposition forms a seed layer on which the MTJ is disposable on the metallic landing pad but not the dielectric pad.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 13, 2018
    Inventors: ANTHONY J. ANNUNZIATA, CHANDRASEKHARAN KOTHANDARAMAN, NATHAN P. MARCHACK, EUGENE J. O'SULLIVAN
  • STRAIN MONITORING OF MRAM ARRAYS
    Publication number: 20180259323
    Abstract: A method is presented for determining strain in a magnetoresistive random access memory (MRAM) structure. The method includes exposing long lines of the MRAM structure to monochromatic light to produce a diffraction pattern, measuring changes in interference fringe spacing in the diffraction pattern, determining the changes in the local strain in the MRAM structure from the measured changes in the interference fringe spacing, and assessing a performance of the MRAM structure from values of the changes in the local strain.
    Type: Application
    Filed: November 2, 2017
    Publication date: September 13, 2018
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Thomas M. Shaw
  • STRAIN MONITORING OF MRAM ARRAYS
    Publication number: 20180259322
    Abstract: A method is presented for determining strain in a magnetoresistive random access memory (MRAM) structure. The method includes exposing long lines of the MRAM structure to monochromatic light to produce a diffraction pattern, measuring changes in interference fringe spacing in the diffraction pattern, determining the changes in the local strain in the MRAM structure from the measured changes in the interference fringe spacing, and assessing a performance of the MRAM structure from values of the changes in the local strain.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 13, 2018
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Thomas M. Shaw
  • MAGNETIC TUNNEL JUNCTION (MTJ) BASED TRUE RANDOM NUMBER GENERATORS (TRNG)
    Publication number: 20180239590
    Abstract: An apparatus is presented for generating a true random number generator (TRNG). The apparatus includes a magnetic tunnel junction (MTJ) device including a first layer, a second layer, and third layer, as well as a bias circuit to bias the MTJ device along with a pulse height discriminator and a time-to-amplitude convertor to generate random bit-streams. The second layer is a barrier layer with an energy barrier height in the order of 20kT, where k is the Boltzmann constant and T is the absolute temperature. Random flipping of an orientation of magnetization of the third layer is induced by thermal fluctuations in the MTJ device.
    Type: Application
    Filed: February 23, 2017
    Publication date: August 23, 2018
    Inventors: Suyog Gupta, Chandrasekharan Kothandaraman, Jonathan Z. Sun
  • Three terminal fuse structure created by oxygen vacancy traps in hafnium-based oxides
    Patent number: 10043584
    Abstract: A fuse structure includes a substrate, a gate dielectric formed on the substrate, a gate electrode formed on the gate dielectric, and first and second source/drain regions formed on the substrate on opposite sides with respect to the gate electrode, wherein the gate dielectric is configured such that a plurality of oxygen vacancies trapping respective charges are formed upon application of a pulse to the gate electrode.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Eduard A. Cartier, Chandrasekharan Kothandaraman
  • INDUCTORS IN BEOL WITH PARTICULATE MAGNETIC CORES
    Publication number: 20180218824
    Abstract: An inductor device includes a conductive coil formed within a dielectric material and having a central core area within the coil. Particles are dispersed within the central core region to reduce eddy current loss and increase energy storage. The particles include magnetic properties.
    Type: Application
    Filed: November 2, 2017
    Publication date: August 2, 2018
    Inventors: Chandrasekharan Kothandaraman, Eugene J. O'Sullivan, Naigang Wang
  • INDUCTORS IN BEOL WITH PARTICULATE MAGNETIC CORES
    Publication number: 20180218823
    Abstract: An inductor device includes a conductive coil formed within a dielectric material and having a central core area within the coil. Particles are dispersed within the central core region to reduce eddy current loss and increase energy storage. The particles include magnetic properties.
    Type: Application
    Filed: January 30, 2017
    Publication date: August 2, 2018
    Inventors: Chandrasekharan Kothandaraman, Eugene J. O'Sullivan, Naigang Wang
  • Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material
    Patent number: 10008536
    Abstract: Methods and devices are provided to construct magnetic devices, such as magnetic random access memory devices, having MTJ (magnetic tunnel junction) structures encapsulated in organic photopatternable dielectric material. For example, a method includes forming an MTJ structure on a semiconductor substrate, encapsulating the MTJ structure in a layer of organic photopatternable dielectric material, patterning the layer of organic photopatternable dielectric material to form a contact opening in the layer of organic photopatternable dielectric material to the MTJ structure, and filling the contact opening with metallic material.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Qinghuang Lin
  • Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material
    Patent number: 10002904
    Abstract: Methods and devices are provided to construct magnetic devices, such as magnetic random access memory devices, having MTJ (magnetic tunnel junction) structures encapsulated in organic photopatternable dielectric material. For example, a method includes forming an MTJ structure on a semiconductor substrate, encapsulating the MTJ structure in a layer of organic photopatternable dielectric material, patterning the layer of organic photopatternable dielectric material to form a contact opening in the layer of organic photopatternable dielectric material to the MTJ structure, and filling the contact opening with metallic material.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Qinghuang Lin
  • THROUGH-SILICON VIA WITH IMPROVED SUBSTRATE CONTACT FOR REDUCED THROUGH-SILICON VIA (TSV) CAPACITANCE VARIABILITY
    Publication number: 20180166381
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.
    Type: Application
    Filed: November 2, 2017
    Publication date: June 14, 2018
    Inventors: John M. SAFRAN, Jochonia N. NXUMALO, Joyce C. LIU, Sami ROSENBLATT, Chandrasekharan KOTHANDARAMAN
  • THREE TERMINAL FUSE STRUCTURE CREATED BY OXYGEN VACANCY TRAPS IN HAFNIUM-BASED OXIDES
    Publication number: 20180122491
    Abstract: A fuse structure includes a substrate, a gate dielectric formed on the substrate, a gate electrode formed on the gate dielectric, and first and second source/drain regions formed on the substrate on opposite sides with respect to the gate electrode, wherein the gate dielectric is configured such that a plurality of oxygen vacancies trapping respective charges are formed upon application of a pulse to the gate electrode.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 3, 2018
    Inventors: Eduard A. Cartier, Chandrasekharan Kothandaraman
  • Transistor structures gated using a conductor-filled via or trench
    Patent number: 9953900
    Abstract: Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A doped region is formed in the substrate. An opening, such as a via or trench, is formed that extends through the doped region and into a portion of the substrate beneath the doped region. A conductive plug in formed in the opening to provide the conductor-filled via or trench. The opening is positioned and dimensioned relative to a position and dimensions of the doped region to divide the doped region into a first section and a second section that is disconnected from the first section by the opening.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: April 24, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John M. Safran, Sami Rosenblatt, Michael S. Cranmer, Chandrasekharan Kothandaraman
  • CRYOGENIC PATTERNING OF MAGNETIC TUNNEL JUNCTIONS
    Publication number: 20180069174
    Abstract: Methods for forming magnetic tunnel junctions and structures thereof include cryogenic etching the layers defining the magnetic tunnel junction without lateral diffusion of reactive species.
    Type: Application
    Filed: September 7, 2016
    Publication date: March 8, 2018
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Nathan P. Marchack, Hiroyuki Miyazoe
  • Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability
    Patent number: 9847290
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: December 19, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John M. Safran, Jochonia N. Nxumalo, Joyce C. Liu, Sami Rosenblatt, Chandrasekharan Kothandaraman
  • MULTI TIME PROGRAMMABLE MEMORIES USING LOCAL IMPLANTATION IN HIGH-K/ METAL GATE TECHNOLOGIES
    Publication number: 20170358588
    Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.
    Type: Application
    Filed: July 12, 2017
    Publication date: December 14, 2017
    Inventors: Takashi Ando, Eduard A. Cartier, Chandrasekharan Kothandaraman
  • MULTI TIME PROGRAMMABLE MEMORIES USING LOCAL IMPLANTATION IN HIGH-K/ METAL GATE TECHNOLOGIES
    Publication number: 20170358587
    Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 14, 2017
    Inventors: Takashi Ando, Eduard A. Cartier, Chandrasekharan Kothandaraman
  • TRANSISTOR STRUCTURES GATED USING A CONDUCTOR-FILLED VIA OR TRENCH
    Publication number: 20170287812
    Abstract: Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A doped region is formed in the substrate. An opening, such as a via or trench, is formed that extends through the doped region and into a portion of the substrate beneath the doped region. A conductive plug in formed in the opening to provide the conductor-filled via or trench. The opening is positioned and dimensioned relative to a position and dimensions of the doped region to divide the doped region into a first section and a second section that is disconnected from the first section by the opening.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 5, 2017
    Inventors: John M. Safran, Sami Rosenblatt, Michael S. Cranmer, Chandrasekharan Kothandaraman
  • Prevention of SRAM burn-in
    Patent number: 9721646
    Abstract: Embodiments are directed to a static random access memory (SRAM) device that prevents burn-in of potentially sensitive information. After an SRAM device is fabricated in a semiconductor material, a heating wire is placed in the layers above portions of the SRAM device. By applying current to the heating wire, a certain temperature is reached for a certain amount of time, and the burn-in of the SRAM is prevented. Other embodiments are also presented.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 1, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chandrasekharan Kothandaraman
  • IMPLANT AFTER THROUGH-SILICON VIA (TSV) ETCH TO GETTER MOBILE IONS
    Publication number: 20170200620
    Abstract: A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.
    Type: Application
    Filed: January 13, 2016
    Publication date: July 13, 2017
    Inventors: Christopher Collins, Mukta G. Farooq, Troy L. Graves-Abe, Brian J. Greene, Robert Hannon, Herbert L. Ho, Chandrasekharan Kothandaraman
  • Magnetic tunnel junction based chip identification
    Patent number: 9705500
    Abstract: The present invention provides integrated circuit chips having chip identification aspects. The chips include magnetic tunnel junction (MTJ) structures, and more specifically, include permanent bit strings used for chip identification and/or authentication. Systems and processes for chip identification are also disclosed herein. The MTJ element structures provided herein can have a defined resistance profile such that the intrinsic variability of the MTJ element structure is used to encode and generate a bit string that becomes a fingerprint for the chip. In some embodiments, an oxygen treatment covering all or a selected portion of an array of MTJ elements can be used to create a mask or secret key that can be used and implemented to enhance chip identification.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Philip L. Trouilloud