Patents by Inventor Chandrika Prasad
Chandrika Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150057459Abstract: The present invention relates to an energy efficient process for the extraction of non-polar lipids from photosynthetically grown micro-algal biomass using low boiling point solvents and utilizing solar energy for heating as well as chilling operations. The invention also relates to improve energy output to input ratio which is the main hurdle in the micro-algal lipid extraction process. The present invention also relates to the recovery of the solvents used for the above processes via solar energy.Type: ApplicationFiled: April 2, 2013Publication date: February 26, 2015Inventors: Pushpito Kumar Ghosh, Sandhya Chandrika Prasad Mishra, Subarna Maiti, Chetan Paliwal, Sanjiv Kumar Mishra, Tonmoy Ghosh, Kaumeel Chokshi, Pankaj Patel, Jitendra Narsinh Bharadia
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Patent number: 8956836Abstract: The present invention provides a simpler and more energy efficient process for the preparation of fatty acid methyl ester (biodiesel) from sun dried whole seed capsules of Jatropha curcas integrated with value addition of seed shells, deoiled cake and crude glycerol co-product stream. More specifically, the invention relates to a method of dispensing with the need for excess methanol recovery through distillation, cost-effective resin treatment for the refining of methyl ester and utilization of co-streams for preparation of high density energy briquettes and Polyhydroxyalkanoate biodegradable polymer in efficient and cost-effective manner.Type: GrantFiled: March 29, 2010Date of Patent: February 17, 2015Assignee: Council of Scientific and Industrial ResearchInventors: Pushpito Kumar Ghosh, Sandhya Chandrika Prasad Mishra, Mahesh Ramniklal Gandhi, Sumesh Chandra Upadhyay, Parimal Paul, Pritpal Singh Anand, Kiritkumar Mangaldas Popat, Anupama Vijaykumar Shrivastav, Sanjiv Kumar Mishra, Neelam Ondhiya, Ramesh Dudabhai Maru, Gangadharan Dyal, Harshad Brahmbhatt, Vinod Boricha, Doongar Ram Chaudhary, Babulal Rebary, Krushnadevsingh Sukhdevsinh Zala
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Patent number: 8741628Abstract: An energy efficient process for the preparation of marine microalgae Chlorella fatty acid methyl ester (CME) from hydrolysate of deoiled cake of Jatropha (JOCH) and crude glycerol co-product stream (GL7 and GL8) along with seawater diluted with tap water (1:2). A small part of the crude glycerol layer in case of JME is processed to recover glycerol for glycerol washing and the otherwise problematic still bottom is utilized for microbial synthesis of PHAs and the rest is utilized for Microalgal conversion of JME byproducts into CME. The remaining part of the methanol-depleted glycerol layer is utilized, along with hydrolysate of the Jatropha deoiled cake (JOCH), for single-stage Microalgal production of lipids by a marine Microalgal isolate (Chlorella sp.) without the need for any other nutrients. Waste streams from the microalgal processes can be discharged directly into agricultural fields as biofertilizer or recycled back in the mass cultivation.Type: GrantFiled: September 22, 2011Date of Patent: June 3, 2014Assignee: Council of Scientific and Industrial ResearchInventors: Pushpito Kumar Ghosh, Sandhya Chandrika Prasad Mishra, Mahesh Ramniklal Gandhi, Sumesh Chandra Upadhyay, Sanjiv Kumar Mishra, Imran Pancha, Anupama Vijaykumar Shrivastav, Deepti Jain, Bhumi Shethia, Subama Maiti, Krushnadevsinh Sukhdevsingh Zala
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Publication number: 20140099684Abstract: The invention teaches the obtained specifications and process of production of engine worthy marine microalgal fatty acid methyl ester (biodiesel) using naturally occurring marine microalgal mats and also marine microalgae cultivated in cost-effective manner in solar salt pans. Utility of co-product streams adds to the attractiveness of the invention.Type: ApplicationFiled: May 22, 2012Publication date: April 10, 2014Applicant: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCHInventors: Sandhya Chandrika Prasad Mishra, Pushpito Kumar Ghosh, Mahesh Ramniklal Gandhi, Sourish Bhattacharya, Subarna Maiti, Sumesh Chandra Upadhyay, Arup Ghosh, Rachapudi Badari Narayana Prasad, Sanjit Kanjilal, Sanjiv Kumar Mishra, Anupama Vijaykumar Shrivastav, Imran Pancha, Chetan Paliwal, Tonmoy Ghosh, Rahul Kumar Maurya, Deepti Jain, Shailesh Kumar Paditar, Abhishek Sahu, Hetal Bosamiya, Krushnadevsinh Zala
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Publication number: 20140038249Abstract: The present invention provides a simpler and more energy efficient process for the preparation of fatty acid methyl ester (biodiesel) from sun dried whole seed capsules of Jatropha curcas integrated with value addition of seed shells, deoiled cake and crude glycerol co-product stream. More specifically, the invention relates to a method of dispensing with the need for excess methanol recovery through distillation, cost-effective resin treatment for the refining of methyl ester and utilization of co-streams for preparation of high density energy briquettes and Polyhydroxyalkanoate biodegradable polymer in efficient and cost-effective manner.Type: ApplicationFiled: March 29, 2010Publication date: February 6, 2014Applicant: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCHInventors: Pushpito Kumar Ghosh, Sandhya Chandrika Prasad Mishra, Mahesh Ramniklal Gandhi, Sumesh Chandra Upadhyay, Parimal Paul, Pritpal Singh Anand, Kiritkumar Mangaldas Popat, Anupama Vijaykumar Shrivastav, Sanjiv Kumar Mishra, Neelam Ondhiya, Ramesh Dudabhai Maru, Gangadharan Dyal, Harshad Brahmbhatt, Vinod Boricha, Doongar Ram Chaudhary, Babulal Rebary, Krushnadevsingh Sukhdevsinh Zala
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Publication number: 20130164799Abstract: An energy efficient process for the preparation of marine microalgae Chlorella fatty acid methyl ester (CME) from hydrolysate of deoiled cake of Jatropha (JOCH) and crude glycerol co-product stream (GL7 and GL8) along with seawater diluted with tap water (1:2). A small part of the crude glycerol layer in case of JME is processed to recover glycerol for glycerol washing and the otherwise problematic still bottom is utilized for microbial synthesis of PHAs and the rest is utilized for Microalgal conversion of JME byproducts into CME. The remaining part of the methanol-depleted glycerol layer is utilized, along with hydrolysate of the Jatropha deoiled cake (JOCH), for single-stage Microalgal production of lipids by a marine Microalgal isolate (Chlorella sp.) without the need for any other nutrients. Waste streams from the microalgal processes can be discharged directly into agricultural fields as biofertilizer or recycled back in the mass cultivation.Type: ApplicationFiled: September 22, 2011Publication date: June 27, 2013Applicant: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCHInventors: Pushpito Kumar Ghosh, Sandhya Chandrika Prasad Mishra, Mahesh Ramniklal Gandhi, Sumesh Chandra Upadhyay, Sanjiv Kumar Mishra, Imran Pancha, Anupama Vijaykumar Shrivastav, Deepti Jain, Bhumi Shethia, Subama Maiti, Krushnadevsinh Sukhdevsingh Zala
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Patent number: 7564118Abstract: A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.Type: GrantFiled: May 2, 2008Date of Patent: July 21, 2009Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan
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Publication number: 20080230891Abstract: A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.Type: ApplicationFiled: May 2, 2008Publication date: September 25, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: H. Bernhard Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan
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Patent number: 7388277Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.Type: GrantFiled: January 12, 2005Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan
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Publication number: 20070252287Abstract: A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads.Type: ApplicationFiled: June 20, 2007Publication date: November 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: H. Pogge, Chandrika Prasad, Roy Yu
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Publication number: 20060278998Abstract: A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads.Type: ApplicationFiled: August 9, 2006Publication date: December 14, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: H. Pogge, Chandrika Prasad, Roy Yu
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Patent number: 7049697Abstract: A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.Type: GrantFiled: June 26, 2003Date of Patent: May 23, 2006Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Chandrika Prasad, Roy Yu
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Patent number: 6998327Abstract: A thin film transfer join process in which a multilevel thin film structure is formed on a carrier, the multilevel thin film structure is joined to a final substrate and then the carrier is removed. Once the carrier is removed, the dielectric material and metallic material that were once joined to the carrier are now exposed. The dielectric material is then etched back so that the exposed metallic material protrudes beyond the dielectric material. Also disclosed is a module made by the foregoing process.Type: GrantFiled: November 19, 2002Date of Patent: February 14, 2006Assignee: International Business Machines CorporationInventors: Jeffrey B. Danielson, Balaram Ghosal, James Kuss, Matthew Wayne Oonk, Chandrika Prasad, Eric Daniel Perfecto, Roy Yu
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Publication number: 20050173800Abstract: A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.Type: ApplicationFiled: June 26, 2003Publication date: August 11, 2005Inventors: H. Pogge, Chandrika Prasad, Roy Yu
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Publication number: 20050121711Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.Type: ApplicationFiled: January 12, 2005Publication date: June 9, 2005Inventors: H. Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan
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Publication number: 20050056943Abstract: A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads.Type: ApplicationFiled: June 8, 2004Publication date: March 17, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: H. Pogge, Chandrika Prasad, Roy Yu
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Publication number: 20050056942Abstract: A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads.Type: ApplicationFiled: September 15, 2003Publication date: March 17, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: H. Pogge, Chandrika Prasad, Roy Yu
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Patent number: 6864165Abstract: A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads.Type: GrantFiled: September 15, 2003Date of Patent: March 8, 2005Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Chandrika Prasad, Roy Yu
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Patent number: 6856025Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.Type: GrantFiled: June 19, 2003Date of Patent: February 15, 2005Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan
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Patent number: 6835589Abstract: A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The MEMS has an anchor portion having a conductor therethrough, by which it is connected to a substrate. The chip is attached to the MEMS substrate in a direction normal to the substrate surface, so as to make a conductive path from the chip to the MEMS. The chip may be attached by bonding the conductor to C4 metal pads formed on the chip, or by bonding the conductor to metal studs on the chip. The MEMS substrate may be thinned before attachment to the chip, or may be removed from the underside of the MEMS. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.Type: GrantFiled: November 14, 2002Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Michel Despont, Ute Drechsler, Chandrika Prasad, Peter Vettiger, Roy Yu