Abstract: A structure for mounting electronic devices. The structure uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.

Abstract: A structure for mounting electronic devices which uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.

Abstract: An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.

Abstract: An apparatus for use in manufacturing a semiconductor device having input-output (IO) lands arranged in an IO array on an IO face includes a body having a plurality of cavities extending from an operating face into the body; the cavities are arranged in a cavity loci array which is in registeration with the IO lands when the apparatus is in a manufacturing position with the operating face generally adjacent the IO face. Each cavity has a depth and a lateral expanse which cooperate to establish a volume defined by a cavity bottom and at least one cavity wall. The volume accommodates an appropriate amount of solder material to establish a measure of the solder material on a facing IO land when the apparatus is in the manufacturing position.

Abstract: A multiple plane pair thin-film structure and a process for the manufacture of that structure. The multiple plane pair thin-film structure is of modular design and manufacture, such that each module comprising the structure is manufactured and tested individually before assembly. The thin film wiring structure is comprised of a plurality of true plane pair thin-film structures. Each such plane pair thin-film structure is manufactured as a module, the functionality of which can be tested for conformity to applicable specifications. Each module is designed and fabricated as a plane pair thin-film structure.

Abstract: A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

Abstract: A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Abstract: A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Abstract: A process for transferring a thin film wiring layer to a substrate in the construction of multilayer chip modules initially provides a sacrificial release layer formed on a surface of a carrier. Directly on the release layer there is formed in inverted fashion a plurality of multilevel thin film structures having at least one wiring path of metallic material exposed on the surface opposite the carrier. An electronic packaging substrate is provided, and solder or other joining material is applied to one or both of the exposed metallic surface of the multilevel thin film structure or the substrate. The multilevel thin film structure is then joined to the substrate so that the attached carrier is remote from the substrate. The release layer is subsequently contacted with an etchant for the release layer so as to remove the carrier from the multilevel thin film structure to produce a multilayer chip module.

Abstract: A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

Abstract: An electrical interconnect structure for connecting a substrate to the next level of packaging or to a semiconductor device. The interconnect structure includes at least two layers of polymeric material, one of the layers having a capture pad and the second of the layers having a bonding pad electrically connected to the capture pad. The bonding pad and the second layer of polymeric material are at the same height so that the bonding pad is level with the second layer of polymeric material. Finally, there is a cap of electrically conducting metallization on the bonding pad and extending beyond the second layer of polymeric material. The cap is of a different composition than the bonding pad.

Abstract: A substrate for an integrated circuit semiconductor package with I/O pins joined to the bottom surface, the improvement being the combination of solder wettable pin pads on the bottom surface of the substrate, I/O pins with a diameter less than the diameters of the pin pads, and a brazing material of an alloy that includes Ag, and a metal selected from the group consisting of In and Sn, and mixtures thereof, that exhibits a mushy zone over a predetermined temperature range, the metal disposed only between the pins and pin pads.

Abstract: A process for bonding an I/O pin to a substrate wherein a mass of brazing material of an alloy that includes Ag and a metal selected from the group consisting of In and Sn and mixtures thereof, that exhibit a mushy zone over a predetermined range, is placed between a pin pad and the bonding surface of an I/O pin, where the diameter of the pin pad exceeds the diameter of the bonding surface of the pin by at least 0.01 inches, heating the resultant assembly to a brazing temperature within the predetermined range to form a mushy state of the brazing material while applying pressure to the pin, and cooling the assembly.

Abstract: A method of forming a brazed joint between conformal surfaces byproviding a Sn gettering metal layer on at least one of the conformal surfaces,placing a mass of a low melting Au Sn alloy between the conformal surfaces,heating the resultant assembly to a temperature in excess of the melting point of the alloy,simultaneously with heating applying a pressure to force the surfaces together to squeeze the major portion of the molten Au-Sn alloy from between the surfaces, and cooling the assembly,the bond between the surfaces formed of a relatively thin higher melting Au-Sn alloy resulting when the major portion of the alloy is removed allowing the remaining Sn to combine with the Sn gettering layer to reduce the relative amount of Sn in the alloy.

Abstract: A method of providing a stress-free metal layer by electroless plating techniques, including the steps of (1) providing a substrate that includes some glass material in at least the surface areas to receive a metal layer, (2) depositing a layer of metal-boron by electroless plating techniques, and (3) heating the resultant metal-boron layer in a non-reacting and/or H.sub.2 environment at a temperature of at least 750.degree. C. for a time sufficient to diffuse the boron to the glass material in the substrate.