Abstract: A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The MEMS has an anchor portion having a conductor therethrough, by which it is connected to a substrate. The chip is attached to the MEMS substrate in a direction normal to the substrate surface, so as to make a conductive path from the chip to the MEMS. The chip may be attached by bonding the conductor to C4 metal pads formed on the chip, or by bonding the conductor to metal studs on the chip. The MEMS substrate may be thinned before attachment to the chip, or may be removed from the underside of the MEMS. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.

Abstract: A thin film transfer join process in which a multilevel thin film structure is formed on a carrier, the multilevel thin film structure is joined to a final substrate and then the carrier is removed. Once the carrier is removed, the dielectric material and metallic material that were once joined to the carrier are now exposed. The dielectric material is then etched back so that the exposed metallic material protrudes beyond the dielectric material. Also disclosed is a module made by the foregoing process.

Abstract: A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.

Abstract: A semi-conductor wafer test or burn-in apparatus having spring contacts made from a shape memory metal which plastically deforms under normal test loading and has a transition temperature at or above or at or below the burn-in temperature.

Abstract: A structure for mounting electronic devices. The structure uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.

Abstract: A process and apparatus are provided for electroplating a film onto a substrate having a top side including a plating surface includes the following steps. Provide a plating tank with an electroplating bath. Provide an anode in the bath. Place a substrate having a plating surface to be electroplated into the electroplating bath connecting surfaces to be plated to a first cathode. Support a second cathode including a portion thereof with openings therethrough extending across the plating surface of the substrate and positioned between the substrate and the anode. Connect power to provide a negative voltage to the first cathode and provide a negative voltage to the second cathode, and provide a positive voltage to the anode.

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Abstract: A process is described for integrating an optoelectronic chip and a driver chip on a substrate, in which a waveguide is built into the substrate and the chips are joined to the substrate using a stud/via alignment technique. The waveguide structure includes a reflector and a channel for transmitting light emitted by the optoelectronic chip. A stud formed on the substrate is aligned to a via formed in a layer on the chip, aligning the chip so that the light reaches the reflector and enters the waveguide. A driver chip may be mounted on the substrate in close proximity to the optoelectronic chip.

Abstract: A method of making a surface planarization is provided using a separate pre-cut or precured film laminated onto a metallized surface to form planarized dielectric coating. The method comprises the steps of: (a) providing a thin film interconnect module with a polyimide adhesive laminated with a pre-cut or pre-cured polyimide lamination film on the top of the polyimide adhesive, the polyimide lamination film being covered with a glass plate; (b) applying pressure and heat in a synchronized format to ensure a uniform curing and gap filling in the thin film module metal for the adhesive layer; and (c) releasing the glass plate to expose a smooth lamination film surface.

Abstract: A process and apparatus are provided for electroplating a film onto a substrate having a top side including a plating surface includes the following steps. Provide a plating tank with an electroplating bath. Provide an anode in the bath. Place a substrate having a plating surface to be electroplated into the electroplating bath connecting surfaces to be plated to a first cathode. Support a second cathode including a portion thereof with openings therethrough extending across the plating surface of the substrate and positioned between the substrate and the anode. Connect power to provide a negative voltage to the first cathode and provide a negative voltage to the second cathode, and provide a positive voltage to the anode.

Abstract: An electronic interconnection assembly having a thin film bonded to either a glass ceramic or to an organic laminate substrate, and a method for attaching a thin film wiring package to the substrate. Provided is the utilization of adhesives which may be processed at significantly lower temperatures so as to avoid damaging components, the wiring package and interconnection joints. Moreover, pursuant to specific aspects, the joining of the thin film to the substrate may be implemented with the utilization of dendrites.

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Abstract: A process is described for integrating an optoelectronic chip and a driver chip on a substrate, in which a waveguide is built into the substrate and the chips are joined to the substrate using a stud/via alignment technique. The waveguide structure includes a reflector and a channel for transmitting light emitted by the optoelectronic chip. A stud formed on the substrate is aligned to a via formed in a layer on the chip, aligning the chip so that the light reaches the reflector and enters the waveguide. A driver chip may be mounted on the substrate in close proximity to the optoelectronic chip.

Abstract: A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.

Abstract: An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.

Abstract: A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. A stud is provided on the front surface of the chip, and a layer with interconnection wiring is formed on a transparent plate. The wiring layer includes a conducting pad on a surface thereof opposite the plate. A second layer is formed on top of the wiring layer, with a via formed therein to expose the conducting pad. The stud and via are then aligned and connected; the front surface of the chip thus contacts the second layer and the stud makes electrical contact with the conducting pad. A chip support is then attached to the device. An interface between the wiring layer and the plate is exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density.

Abstract: A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.

Abstract: An electronic component structure assembly comprising a thin film structure bonded to a multilayer ceramic substrate (MLC) using solder connections and wherein a non-conductive, compliant spacer preferably with a layer of thermoplastic adhesive on each surface thereof is interposed between the underlying MLC carrier and overlying thin film structure. The spacer includes a pattern of through-holes which corresponds to opposing contact pads of the thin film structure and MLC. The contact pads of at least one of the thin film structure or MLC have posts (e.g., metallic) thereon and the posts extend partly into the spacer through-holes whereby the height of the posts are greater than the thickness of the adhesive. The posts of the MLC have solder bumps thereon. After reflow under pressure the thin film structure is electrically and mechanically connected to the MLC and the join method has been found to provide a reliable and cost-effective process. The joined components also have enhanced operating life.

Abstract: A method and structure for providing top-to-bottom repair of a defective I/O net in a thin film transfer and join process. At least one C4 location and at least one capture pad are provided on a thin film substrate. The substrate is preferably ceramic. The C4 location of the defective net is severed by removal of a delete strap. The corresponding solder connection of the associated capture pad is also removed. A spare C4 location and capture pad are connected to provide a Z-repair line imbedded in the TF wiring structure. The Z-repair line is wired to the defective net.