Abstract: A system and method for effectively performing an integrated segmentation procedure comprises an image segmenter that includes a texture modeler, a contrast modeler, and a model integrator. The texture modeler creates a texture model based upon an original image. Similarly, the contrast modeler creates a contrast model based upon the original image. The model integrator then performs a model integration procedure to create a final segmented image by integrating the texture model and the contrast model according to a calculated texture model metric. A processor of an electronic device typically controls the image segmenter to perform the integrated segmentation procedure.

Abstract: An antenna apparatus includes a metal shell, a circuit board parallel to the metal shell which forms a space between the circuit board and the shell, a tunable matching circuit mounted in the space with an terminal electrically connected to the shell, and an capacitive feed coupling antenna mounted on the circuit board. The capacitive feed coupling antenna includes a coupling ground strip mounted on the circuit board and a feed strip. The feed strip includes a first portion and a second portion mounted on the circuit board with a portion extending along an edge of the circuit board. The first portion is electrically interconnected between the other terminal of the tunable matching circuit and the second portion.

Abstract: The disclosure provides a display device, comprising a connecting component, a base, a display monitor and a sliding unit. The connecting component includes a first end and a second end opposite to each other. The first end of the connecting component is pivoted on the base. The sliding unit is disposed on the display monitor. The second end of the connecting component is slidably pivoted on the sliding unit.

Abstract: Systems, methods and computer storage mediums securely authenticate an identity of an individual based on a pattern that is traced by the individual. Embodiments of the present disclosure relate to prompting an individual with a pattern to trace when attempting to authenticate the identity of the individual during an identity authentication session. Motion-based behavior data that is generated by motions executed by the individual as the individual traces the pattern is captured via a motion-capturing sensor. The motion-based behavior data is unique to the individual and has a low likelihood of being duplicated by an unauthorized individual attempting to fraudulently pose as the individual. The captured motion-based behavior data is compared to previously captured motion-based behavior data from previous traces of the pattern completed by the individual.

Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Abstract: A memory cell and method includes a first electrode formed in an opening in a first dielectric layer, the first dielectric layer being formed on a substrate including a metal layer, the opening being configured to allow physical contact between the first electrode and the metal layer, the first electrode having a first width W1 and extending a distance beyond a region defined by the opening, a resistive layer formed on the first electrode and having substantially the first width W1, a capping layer, having a second width W2 less than the first width W1, formed on the resistive layer, a second electrode formed on the capping layer and having substantially the second width W2, a first composite spacer region having at least two different dielectric layers formed on the resistive layer between the first width W1 and the second width W2, and a via coupled to the second electrode.

Abstract: A system for performing a scene representation procedure includes an image manager that processes source images from a given scene to define subscenes in the source images. The image manager creates an image understanding graph for each of the source images, and also creates a scene representation graph for each of the source images based upon the corresponding subscenes and certain image characteristics. The image manager further generates an integrated scene representation to represent all of the source images with a single representation. A processor of an electronic device controls the image manager to perform the scene representation procedure.

Abstract: An exemplary method of creating a target storage layout table referenced for partitioning a storage space of a storage device includes following steps: identifying defective storage areas in the storage space of the storage device, and accordingly generating an identification result; and creating the target storage layout table according to the identification result.

Abstract: A method of improving accuracy and reliability of motion estimation is described herein. In one aspect, a 2D neighborhood of phase correlation peak is approximated with an outer-product of two 1D vectors to eliminate the sub-pixel error. In another aspect, estimation of reliability is improved. In yet another aspect, two-pass phase correlation is implemented to eliminate sub-pel motion bias.

Abstract: Methods and apparatus supporting an electrical connection are disclosed. Systems previously equipped with wire interfaces, such as battery terminals, can be equipped with a connector assembly to significantly reduce a hazard of electrical shock to a user. The connector assembly includes a stress relief component that attenuates a force, applied to the stress relief component, to reduce its effect on the connector assembly. By attenuating the force, the connector assembly maintains a substantially fixed position relative to the battery pack component and mitigates a potential for disruption in electrical connectivity. Techniques disclosed herein benefit users of battery packs or other devices as well as manufacturers by increasing safety, reliability, and ergonomics.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate structures having asymmetric sidewalls including a tall side and a short side. Adjacent ones of the plurality of gate structures are separated by a tall side-tall side region and a short side-short side region. The method further comprises forming a spacer layer over the plurality of gate structures and a bottom surface of the tall side-tall side region and the short side-short side region, depositing an oxide layer over the spacer layer, etching the bottom surface portions of the oxide layer, and selectively etching the sidewall portions of the oxide layer in the tall side-tall side region.

Abstract: A riser of a compound bow includes a lower section and an upper section. The upper section has an end section and a connection section which is connected to the lower section by engagement of pins and pin holes of the two respective connection ends. The connection is further reinforced by way of welding. The end section is further connected with the connection section by engagement of pins and pin holes of the two respective connection ends. The connection is further reinforced by way of welding. The riser is strong and saves material.

Abstract: Phase correlation is an established method for computing motion which relies on the ability to find peaks in a computed phase correlation surface. Two methods to improve the ability to detect peaks in the phase correlation surface are described herein. The first method applies a theoretically-derived and spatially-varying gain to the phase correlation surface. The gain compensates for peaks whose amplitudes have been decreased due to windowing effects; such effects are unavoidable in phase correlation. The second method uses concepts from matched filters to improve detection of peaks whose amplitudes are diminished due to a spreading of the peak energy into surrounding positions in the phase correlation surface. Peak detection filters allow such low-amplitude peaks to be properly detected. It is possible to use only the first method, or only the second method or both methods combined.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate structures having asymmetric sidewalls including a tall side and a short side. Adjacent ones of the plurality of gate structures are separated by a tall side-tall side region and a short side-short side region. The method further comprises forming a spacer layer over the plurality of gate structures and a bottom surface of the tall side-tall side region and the short side-short side region, depositing an oxide layer over the spacer layer, etching the bottom surface portions of the oxide layer, and selectively etching the sidewall portions of the oxide layer in the tall side-tall side region.

Abstract: A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified.

Abstract: The present disclosure discloses a method of fabricating a semiconductor device. A first layer is formed over a substrate. A patterned second layer is then formed over the first layer. The patterned second layer includes an opening. A spacer material is then deposited in the opening, thereby reducing the opening in a plurality of directions. A direction-specific trimming process is performed to the spacer material and the second layer. Thereafter, the first layer is patterned with the second layer.

Abstract: The present invention provides surface plasmon resonance (SPR) based sensing systems and methods for rapid, sensitive, and real-time analysis of analyte secretion from living cells. In one embodiment, the SPR based sensing device of the present invention comprises at least one cell culture module for culturing living cells, wherein the cell culture module is configured so that analytes secreted from the living cells can be released onto a SPR sensing surface.

Abstract: A touch-sensing display device includes a display panel, a touch panel, a driver unit, and a flexible printed circuit board. The touch panel is disposed on the display panel, and the driver unit is disposed on the display panel to provide driving signals and drive the display panel and the touch panel. The flexible printed circuit board connects the display panel to a system main board.

Abstract: A mobile station operating in a wireless network system comprising a plurality of base stations is disclosed. A communication unit receives the messages from a first base station of the wireless network system to which the mobile station is currently connected. A signal detection unit detects a first averaged signal strength corresponding to the messages received from the first base station. A processor determines a scan period according to the first averaged signal strength, performing a background scan, at intervals during the scan period, to monitor messages from the plurality of base stations within the wireless network system.

Abstract: A wafer alignment system is provided for performing a unidirectional scan-exposure. The wafer alignment system includes a plurality of wafer stages successively moving from a first position to a second position of a base cyclically. The wafer alignment method also includes an encoder plate having a first opening and a second opening. Further, the wafer alignment system includes a plurality of encoder plate readers and a plurality of wafer stage fiducials on the wafer stages. Further, the wafer alignment system also includes an alignment detection unit above the first opening of the encoder plate.