Patents by Inventor Chang-Chia HUANG
Chang-Chia HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160071744Abstract: Some embodiments of the present disclosure provide a method of manufacturing a device. The method includes providing a carrier, the carrier including a top surface, covering a portion of the top surface with a plurality of active dies, disposing a protrudent band over a periphery of the carrier, wherein the protrudent band includes a rim shaped along the contour of the carrier, and forming a molding compound over the carrier to cover the plurality of active dies. A method for determining a width of the protrudent band of a device described herein is also provided.Type: ApplicationFiled: November 10, 2015Publication date: March 10, 2016Inventors: YU-CHIH LIU, CHANG-CHIA HUANG, SHIH-YEN LIN, CHIN-LIANG CHEN, KUAN-LIN HO, WEI-TING LIN
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Publication number: 20160035591Abstract: Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill.Type: ApplicationFiled: October 14, 2015Publication date: February 4, 2016Inventors: Chang-Chia Huang, Chen-Shien Chen, Sheng-Yu Wu, Tin-Hao Kuo, Yen-Liang Lin
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Patent number: 9209046Abstract: A method of manufacturing a WLP semiconductor structure includes several operations. One of the operations is providing a carrier and the carrier includes a top surface. One of the operations is covering a portion of the top surface with a plurality of active dies. One of the operations is disposing a protrudent band on a periphery of the carrier, wherein the protrudent band includes a rim shaped along the contour of the carrier. One of the operations is forming a molding compound on the carrier to cover the plurality of active dies.Type: GrantFiled: October 2, 2013Date of Patent: December 8, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Chih Liu, Chang-Chia Huang, Shih-Yen Lin, Chin-Liang Chen, Kuan-Lin Ho, Wei-Ting Lin
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Publication number: 20150348877Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.Type: ApplicationFiled: September 2, 2014Publication date: December 3, 2015Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu
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Publication number: 20150325542Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.Type: ApplicationFiled: July 21, 2015Publication date: November 12, 2015Inventors: Yen-Liang Lin, Yu-Jen Tseng, Chang-Chia Huang, Tin-Hao Kuo, Chen-Shien Chen
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Patent number: 9165796Abstract: Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill.Type: GrantFiled: August 13, 2014Date of Patent: October 20, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Liang Lin, Chang-Chia Huang, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
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Patent number: 9105530Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar width, and the UBM width is greater than the pillar width.Type: GrantFiled: May 29, 2013Date of Patent: August 11, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Liang Lin, Yu-Jen Tseng, Chang-Chia Huang, Tin-Hao Kuo, Chen-Shien Chen
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Publication number: 20150093856Abstract: A method of manufacturing a WLP semiconductor structure includes several operations. One of the operations is providing a carrier and the carrier includes a top surface. One of the operations is covering a portion of the top surface with a plurality of active dies. One of the operations is disposing a protrudent band on a periphery of the carrier, wherein the protrudent band includes a rim shaped along the contour of the carrier. One of the operations is forming a molding compound on the carrier to cover the plurality of active dies.Type: ApplicationFiled: October 2, 2013Publication date: April 2, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: YU-CHIH LIU, CHANG-CHIA HUANG, SHIH-YEN LIN, CHIN-LIANG CHEN, KUAN-LIN HO, WEI-TING LIN
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Patent number: 8987915Abstract: A method of manufacturing a semiconductor structure includes several operations. The several operations include placing a plurality of dies on a carrier; defining a first zone and a second zone in a top surface of the carrier; calculating a first coverage ratio in the first zone; calculating a second coverage ratio in the second zone; disposing a dummy block on a specified location of the top surface of the carrier if the difference between the first coverage ratio and the second coverage ratio is greater than a predetermined value; forming a molding compound on the carrier.Type: GrantFiled: August 29, 2013Date of Patent: March 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chen-Hua Yu, Mirng-Ji Lii, Chung-Shi Liu, Chang-Chia Huang, Chih-Wei Lin, Ming-Da Cheng
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Publication number: 20150061162Abstract: A method of manufacturing a semiconductor structure includes several operations. The several operations include placing a plurality of dies on a carrier; defining a first zone and a second zone in a top surface of the carrier; calculating a first coverage ratio in the first zone; calculating a second coverage ratio in the second zone; disposing a dummy block on a specified location of the top surface of the carrier if the difference between the first coverage ratio and the second coverage ratio is greater than a predetermined value; forming a molding compound on the carrier.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: CHEN-HUA YU, MIRNG-JI LII, CHUNG-SHI LIU, CHANG-CHIA HUANG, CHIH-WEI LIN, MING-DA CHENG
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Patent number: 8922006Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 ?m. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer.Type: GrantFiled: July 27, 2012Date of Patent: December 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Liang Lin, Chen-Shien Chen, Tin-Hao Kuo, Sheng-Yu Wu, Tsung-Shu Lin, Chang-Chia Huang
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Publication number: 20140346673Abstract: Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill.Type: ApplicationFiled: August 13, 2014Publication date: November 27, 2014Inventors: Yen-Liang Lin, Chang-Chia Huang, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
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Patent number: 8883628Abstract: A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.Type: GrantFiled: June 25, 2013Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Chun Chuang, Chang-Chia Huang, Tsung-Shu Lin, Chen-Cheng Kuo, Chen-Shien Chen
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Patent number: 8866285Abstract: A device includes a polymer, a device die in the polymer, and a plurality of Through Assembly Vias (TAVs) extending from a top surface to a bottom surface of the polymer. A bulk metal feature is located in the polymer and having a top-view size greater than a top-view size of each of the plurality of TAVs. The bulk metal feature is electrically floating. The polymer, the device die, the plurality of TAVs, and the bulk metal feature are portions of a package.Type: GrantFiled: September 5, 2012Date of Patent: October 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Chang Hu, Chang-Chia Huang, Ching-Wen Hsiao, Chen-Shien Chen
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Publication number: 20140077365Abstract: An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.Type: ApplicationFiled: May 29, 2013Publication date: March 20, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Liang Lin, Yu-Jen Tseng, Chang-Chia Huang, Tin-Hao Kuo, Chen-Shien Chen
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Publication number: 20140061937Abstract: A device includes a polymer, a device die in the polymer, and a plurality of Through Assembly Vias (TAVs) extending from a top surface to a bottom surface of the polymer. A bulk metal feature is located in the polymer and having a top-view size greater than a top-view size of each of the plurality of TAVs. The bulk metal feature is electrically floating. The polymer, the device die, the plurality of TAVs, and the bulk metal feature are portions of a package.Type: ApplicationFiled: September 5, 2012Publication date: March 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Chang Hu, Chang-Chia Huang, Ching-Wen Hsiao, Chen-Shien Chen
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Publication number: 20130288473Abstract: A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.Type: ApplicationFiled: June 25, 2013Publication date: October 31, 2013Inventors: Yao-Chun Chuang, Chang-Chia Huang, Tsung-Shu Lin, Chen-Cheng Kuo, Chen-Shien Chen
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Publication number: 20130277828Abstract: Methods and apparatus for a solder mask trench used in a bump-on-trace (BOT) structure to form a semiconductor package are disclosed. A solder mask layer is formed on a trace and on a substrate. An opening of the solder mask layer, called a solder mask trench, is formed to expose the trace on the substrate. The solder mask trench has a width about a size of a diameter of a solder bump. A solder bump is landed directly on the exposed trace to connect a chip to the trace by an interconnect. With the formation of the solder mask trench, the trace exposed in the solder mask trench have a better grab force, which reduces the trace peeling failure for the semiconductor package. A plurality of solder mask trench rings may be formed in a package.Type: ApplicationFiled: April 18, 2012Publication date: October 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chang-Chia Huang, Tsung-Shu Lin, Han-Ping Pu, Yen-Liang Lin, Sheng-Hsiang Chiu
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Publication number: 20130256870Abstract: A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface of the metal trace.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chang-Chia HUANG, Tsung-Shu LIN, Ming-Da CHENG, Wen-Hsiung LU, Bor-Rung SU
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Publication number: 20130256874Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 ?m. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer.Type: ApplicationFiled: July 27, 2012Publication date: October 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Liang Lin, Chen-Shien Chen, Tin-Hao Kuo, Sheng-Yu Wu, Tsung-Shu Lin, Chang-Chia Huang