Abstract: Provided is a bitline isolation circuit in a sense amplifier generating an isolation signal for controlling an isolation circuit to isolate a connection between a bitline sense amplifier and a bitline at the beginning of sensing of a read operation, according to an output of a control unit generating an isolation control signal, a start signal of the bitline sense amplifier, and a memory block select signal. The control unit includes: a write pulse generation unit for generating a first control signal, according to a first input signal as a bank address signal latched for every clock, a second input signal generated when a write or a read command is inputted, and a third input signal having a different level according to the read or the write command; and an isolation control signal generation unit for generating the isolation control signal, according to the first control signal and the second control signal having a different level according to a row active operation and a precharge operation.

Abstract: A semiconductor memory device for reducing data line length includes a plurality of data input strobe signal generation units each of which for generating a plurality of data input strobe signals based on a plurality of data input control code signals; and a plurality of data coders one-to-one corresponded to the plurality of data input strobe signal generation units for outputting data to a plurality of global input/output lines according to the plurality of data input strobe signals.

Abstract: A memory cell test circuit for use in a semiconductor memory device having a plurality of banks connected to a plurality of global input/output lines, including: a plurality of bank switching units for transferring data outputted from the plurality of banks to the plurality of global input/output lines based on a test mode signal and a plurality of control clock signals; a logic operation unit for performing a logic operation to the data outputted to the plurality of global input/output lines and for outputting a result of the logic operation to a test global input/output line; and a switching unit coupled to the test global input/output line and the plurality of global input/output lines for selectively passing data of the test global input/output line and data of the global input/output lines based on the test mode signal and the plurality of control clock signals.

Abstract: Disclosed is a bit line precharge signal generator for a memory device, which reduces a resistance component of a signal line by shortening the length of a signal line transferring bit line signals, and reduces an RC time delay. Control signal generator generates a first control signal. A plurality of bit line precharge signal drivers are controlled by first control signal from control signal generator. Each of the bit line precharge signal drivers applies a second signal to the bit line sense amplifier array which is adjacent to bit line precharge signal driver. By using bit line precharge signal generator, a necessary operation is performed within a short time, and unneccessary signal lines are reduced. As a result, a total layout area is reduced.

Abstract: A row redundancy circuit comprises a fuse box group array, a redundant row predecoder and a redundant sub-row decoder. The fuse box group array which comprises a plurality of fuse box groups detects whether repaired row addresses are applied. Each fuse box group consists of at least two or more fuse boxes to detect row addresses. The redundant row predecoder performs a logic operation on an output signal from each fuse box group to selectively activate redundant main wordlines each of which correspondings to a plurality of redundant sub-wordlines. The redundant sub-row decoder performs a logic operation on output signals from the fuse box groups, which are classified into group signals corresponding to the number of fuse boxes in each fuse box group, to output a boosting signal for selectively activating the plurality of sub-wordlines corresponding to the each redundant main wordline.

Abstract: Disclosed is a bit line precharge signal generator for a memory device, which reduces a resistance component of a signal line by shortening the length of a signal line transferring bit line signals, and reduces an RC time delay. Control signal generator generates a first control signal. A plurality of bit line precharge signal drivers are controlled by first control signal from control signal generator. Each of the bit line precharge signal drivers applies a second signal to the bit line sense amplifier array which is adjacent to bit line precharge signal driver. By using bit line precharge signal generator, a necessary operation is performed within a short time, and unneccessary signal lines are reduced. As a result, a total layout area is reduced.

Abstract: A row redundancy circuit comprises a fuse box group array, a redundant row predecoder and a redundant sub-row decoder. The fuse box group array which comprises a plurality of fuse box groups detects whether repaired row addresses are applied. Each fuse box group consists of at least two or more fuse boxes to detect row addresses. The redundant row predecoder performs a logic operation on an output signal from each fuse box group to selectively activate redundant main wordlines each of which correspondings to a plurality of redundant sub-wordlines. The redundant sub-row decoder performs a logic operation on output signals from the fuse box groups, which are classified into group signals corresponding to the number of fuse boxes in each fuse box group, to output a boosting signal for selectively activating the plurality of sub-wordlines corresponding to the each redundant main wordline.

Abstract: A row redundancy circuit comprises a fuse box group array, a redundant row predecoder and a redundant sub-row decoder. The fuse box group array comprises a plurality of fuse box groups including at least two or more fuse boxes to detect row addresses. The redundant row predecoder performs a logic operation on an output signal from the fuse box groups to selectively activate a redundant main wordline corresponding to a plurality of redundant sub-wordlines. The redundant sub-row decoder performs a logic operation on output signals from the fuse box groups, which are classified into group signals corresponding to the number of fuse boxes in each fuse box group, to output a boosting signal for selectively activating the plurality of sub-wordlines corresponding to the each redundant main wordline.

Abstract: A memory repair circuit uses an antifuse of MOS structure, capable of repairing defective cells by constructing the antifuse by MOS transistors and programming the antifuse circuit properly. The memory repair circuit comprises a plurality of antifuse devices, each programmed when a power voltage and a negative voltage are supplied respectively to a first electrode and a second electrode thereof; a latch for detecting and latching program states of the antifuse devices; and a redundancy block for replacing a defect cell with a redundancy cell depending on the output of the latch.

Abstract: A repair circuit substitutes a defective cell with a redundancy cell. For the purpose, the repair circuit includes an antifuse programmed by a voltage difference of both ends thereof, a programming circuit for programming the antifuse, a detection circuit for detecting whether the antifuse is programmed or unprogrammed by using a first and a second power stabilization signal of a power up reset circuit, wherein the detection is performed during a power stabilization period or after the power stabilization period, a latch circuit for latching the result of the detection to thereby generate an output signal, and a redundancy circuit having a redundancy cell for repairing the defective cell in response to the output signal of the latch circuit.

Abstract: An antifuse repair circuit is disclosed for selectively programming a specific antifuse to replace a defective cell with a redundant cell.

Abstract: An antifuse circuit provides a stabilized high voltage to an antifuse programming circuit through the use of an NC pin which is not used in the chip operation.

Abstract: A semiconductor device with an electrostatic discharge (ESD) protective circuit is disclosed. In this semiconductor device with an ESD protective circuit, an n-well guard ring is formed around an NMOS field transistor of a data input buffer or around an NMOS transistor of a data output buffer. The n-well guard ring is strapped to an n-well of a PMOS field transistor and to an n-well of a PMOS transistor, and thus a PNPN path is formed toward the PMOS transistor at a positive mode of the ground voltage. Therefore, the electrical resistance between the wells of the NMOS transistors and the PMOS transistors can be reduced, thereby improving the characteristics of the ESD protective circuit and a latch-up device. Further the layout area is reduced, and thus, the characteristics and the reliability of the semiconductor device are improved.

Abstract: A repair circuit substitutes a defective cell with a redundancy cell. For the purpose, the repair circuit includes an antifuse programmed by a voltage difference of both ends thereof, a programming circuit for programming the antifuse, a detection circuit for detecting whether the antifuse is programmed or unprogrammed by using a first and a second power stabilization signal of a power up reset circuit, wherein the detection is performed during a power stabilization period or after the power stabilization period, a latch circuit for latching the result of the detection to thereby generate an output signal, and a redundancy circuit having a redundancy cell for repairing the defective cell in response to the output signal of the latch circuit.

Abstract: An antifuse circuit provides a stabilized high voltage to an antifuse programming circuit through the use of an NC pin which is not used in the chip operation.

Abstract: A memory repair circuit uses an antifuse of MOS structure, capable of repairing defective cells by constructing the antifuse by MOS transistors and programming the antifuse circuit properly. The memory repair circuit comprises a plurality of antifuse devices, each programmed when a power voltage and a negative voltage are supplied respectively to a first electrode and a second electrode thereof; a latch for detecting and latching program states of the antifuse devices; and a redundancy block for replacing a defect cell with a redundancy cell depending on the output of the latch.

Abstract: An antifuse repair circuit is disclosed for selectively programming a specific antifuse to replace a defective cell with a redundant cell.