Abstract: A metal wiring for semiconductor devices having a double-layer passivation film structure consisting of an intermetallic compound layer formed on a copper thin film and made of a metal reacting with copper to form an intermetallic compound and a metal nitride layer formed over the intermetallic compound. This double-layer passivation film structure is obtained by depositing a metal layer, capable of reacting with copper to form an intermetallic compound, over the copper wiring, and annealing the metal layer in a nitrogen atmosphere, thereby forming an intermetallic compound layer over the copper wiring. By virtue of the double-layer passivation film structure, the copper wiring has a great improvement in the reliability. A metal silicide layer is formed between a diffusion region and a diffusion barrier layer in the contact hole of the semiconductor device. The diffusion barrier layer, which is formed on an insulating layer doped with nitrogen ions, is changed into a metal nitride film.

Abstract: A method of forming a semiconductor device by concurrently forming both single-trenched small field regions and double-trench-extension large field regions, and the device so formed.

Abstract: A MOSFET in accordance with this invention includes: a metal silicide layer formed on a impurity region and on the upper surface of a gate electrode; a metal silicide nitride layer formed on the metal silicide layer; and a metal nitride layer formed on the metal silicide nitride layer. The process for formation of a conductive layer includes the steps of: (a) forming an impurity region in a semiconductor substrate; (b) forming a metal layer on the impurity region; (c) carrying out a heat treatment under an inert gas atmosphere to form a metal silicide of metastable phase; and (d) carrying out a heat treatment under an nitrogen gas atmosphere so as for the metal silicide of the metastable phase to be phase-transited to a stable phase.

Abstract: A process for forming an MOS semiconductor device having an LDD structure is disclosed, which may include the steps of: forming a first insulating layer on a semiconductor substrate; forming a conductive layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a third insulating layer on the second insulating layer; forming an etch inhibiting layer pattern for forming an over-sized gate on a relevant area of the second insulating layer; removing the second and third insulating layers and the conductive layer excluding the portions protected from the etch inhibiting layer, so as to form a stacked pattern consisting of the residual second insulating layer/the third insulating layer/the conductive layer; forming a first impurity ion buried layer on a relevant portion of the semiconductor substrate utilizing the stacked pattern for formation of a source/drain region; removing the etch inhibiting layer; removing an edge portion of the remaining second insulating layer

Abstract: A recess is formed (dug) into the surface of a substrate to form a gate channel in the recess, so that a monocrystalline source/drain region can be formed at a level higher than that of the channel. The process includes the steps of: (a) forming an insulating layer and an oxidation preventing layer on a semiconductor substrate, and removing the oxidation preventing layer of a channel region of the transistor by an etching process; (b) forming an oxide layer on the channel region of the transistor by thermally oxidizing the semiconductor substrate, removing the oxidation preventing layer, and carrying out a first ion implantation on the whole surface; (c) removing the oxide layer, and forming the channel of the transistor in the form of a recess so as for the recess to be positioned lower than the surface of the substrate; (d) forming a gate electrode in the recess; and (e) carrying out a second ion implantation on the whole surface, and carrying out a heat treatment to form a source/drain region.

Abstract: The present invention provides a process for cleaning semiconductor devices which enables the contamination of copper to maintained under a level of about 10.sup.9 atoms/cm.sup.2 to meet the qualification of DRAMs of equal to or greater than 64M bits in capacity by means of supplying O.sub.3 to a solution, resulting in great reproducibility and reliability. According to the present invention, a mechanism for removing a copper impurity in a semiconductor device uses oxygen to form a cupric oxide, which forms a cupric fluoride, which is then removed from the solution.

Abstract: A method for isolating semiconductor regions so that unit elements may be electrically insulated. A disclosed method includes the steps of: forming a pad oxide layer and a nitride layer on a silicon substrate, and forming an active region pattern; exposing the pad oxide to HF to remove a portion of the pad oxide, and depositing polysilicon so that pad oxide as the path for the diffusion of oxygen during the oxidation is not exposed to the oxidizing atmosphere; forming a nitride layer side wall on the side of field region to increase the distance between field oxide region and active region; and carrying out a field channel stop ion implantation after the completion of the first field oxidation and after removing the side wall of nitride layer and before a second field oxidation process.

Abstract: A process for formation of an MOS semiconductor device having an LDD structure is disclosed, which may include the steps of: forming an active region and an isolation region on a semiconductor substrate; forming a first insulating layer on the surface of the substrate; forming a gate electrode on the first insulating layer in the active region; foxing a layer of a heat sensitive fluid material on the gate electrode; carrying out a first ion implantation into the substrate; carrying out a first heat treatment on the heat sensitive layer; carrying out a second ion implantation into the substrate; removing the residual fluid material; forming a second insulating layer on the whole surface of the wafer; and carrying out a second heat treatment on the wafer.

Abstract: In the method of present invention, an LDD MOSFET is formed without using a side wall spacer as an ion implantation inhibiting layer.

Abstract: A method for isolating elements in a silicon semiconductor device is disclosed. The invention discloses the steps of: (1) forming a thermal silicon oxide layer on a silicon substrate, depositing a layer of polysilicon, and depositing a first silicon nitride layer thereon, (2) patterning an active region and a field region, and etching the thermal oxidation layer, the polysilicon layer and the first silicon nitride layer on the field region to forth an active region pattern, (3) depositing a second silicon nitride layer, and, thereupon, depositing a silicon oxide layer, (4) etching back the oxide layer by application of a reactive ion etch technique, forming a silicon oxide side wall on the side of the active region pattern, and etching back the second silicon nitride layer using the oxide side wall as a mask to expose the silicon substrate, (5) removing the oxide side wall, and performing a channel stop field ion implantation, and (6) performing a field oxidation process to form a field oxide layer.

Abstract: A process for formation of a multi-stack type capacitor is disclosed, which comprises: steps of forming a polysilicon layer 5 on a source, forming a dielectric 5a, forming a layer 6, and forming a dielectric layer 6a in the cited order; step of self-aligning a contact pattern for connecting the layer 5 and the layer 7; step of carrying out an etching so as for the layer 5 and the layer 7 to be connected later; steps of forming the layer 7, and forming a dielectric layer 7a; step of self-aligning a contact pattern for connecting the layer 6 and a layer 8; step of carrying out an etching so as for the layer 6 and the layer 8 to be connected later; and step of forming the layer 8, the above steps being repeated in order to form a multi-stack type capacitor of a sandwiched form. According to the present invention, the device is protected from the etch damage, and is suitable for use in a high density memory device.