Abstract: A method of providing neighbor base station information via a mobile subscriber station in a broadband wireless access system is disclosed. In providing neighbor base station information (S316) to a serving base station from a mobile subscriber station in a broadband wireless access system, the present invention includes the steps of performing a scanning and a synchronization (S312, S313) on a mobile base station based on information provided from the serving base station (S311) and transmitting the neighbor base station information acquired from the scanning and the synchronization to the serving base station (S316) regardless of a presence or non-presence of a request from the serving base station. Accordingly, the present invention can efficiently transmit the neighbor base station signal intensity and frame information acquired by the mobile subscriber station.

Abstract: In a case where the serving base station sets Scan Duration of the MOB-SCN-RSP message to 0 to reject a scan request from the mobile subscriber station as seen from above, the following two problems occur. First, because the mobile subscriber station does not know the reason why the scan request is denied, it may request scanning of neighbor base stations again by sending a scan request message to the serving base station before performing periodic ranging. In this case, the serving base station must reject again the scan request from the mobile subscriber station through a scanning response message, and thus an unnecessary exchange of a MAC message, and thus an unnecessary exchange of station and the serving base station. Such an unnecessary MAC message exchange becomes one of the causes of the waste of wireless resources and deteriorates the MAC processing efficiency.

Abstract: A method of associating a mobile station to a base station in a wireless communication system comprises transmitting to a serving base station a scanning request message comprising an association indicator. The method also comprises receiving from the serving base station a scanning response message comprising a rendezvous time associated with a neighboring base station for initiating ranging with the neighboring base station, wherein the serving base station communicates an association notification to the neighboring base station, the association notification comprising the rendezvous time. The method also comprises associating with the neighboring base station by transmitting a ranging request after passing of the rendezvous time determined from a transmission time of the scanning response message from the neighboring base station, wherein the rendezvous time is associated with a time the neighboring base station is expected to provide a non-contention based ranging opportunity for the mobile station.

Abstract: A method of performing a ranging process between a base station and a mobile station in sleep mode in a wireless access system, wherein the base station provides the mobile station with an initial notification of a periodic ranging time that occurs during a sleep time interval and during which the mobile station is to perform the ranging process, the initial notification included in a first message, the first message indicating whether the mobile station should terminate sleep mode to receive downlink data, and wherein the base station provides the mobile station with subsequent notifications of periodic ranging times that occur during the sleep time interval, the subsequent notifications indicated in a second message, the second message transmitted to the mobile station as part of the ranging process such that the mobile station performs a plurality of ranging processes within the sleep time interval.

Abstract: A method of performing a ranging process between a base station and a mobile station in sleep mode in a wireless access system, wherein the base station provides the mobile station with an initial notification of a periodic ranging time that occurs during a sleep time interval and during which the mobile station is to perform the ranging process, the initial notification included in a first message indicating whether the mobile station should terminate sleep mode to receive downlink data, and wherein the base station provides the mobile station with subsequent notifications of periodic ranging times that occur during the sleep time interval, the subsequent notifications indicated in a second message, the second message transmitted to the mobile station as part of the ranging process such that the mobile station performs a plurality of ranging processes within the sleep time interval.

Abstract: A method of performing a ranging process between a base station and a mobile station in sleep mode in a wireless access system, wherein the base station provides the mobile station with an initial notification of a periodic ranging time that occurs during a sleep time interval and during which the mobile station is to perform the ranging process, the initial notification included in a first message indicating whether the mobile station should terminate sleep mode to receive downlink data, and wherein the base station provides the mobile station with subsequent notifications of periodic ranging times that occur during the sleep time interval, the subsequent notifications indicated in a second message, the second message transmitted to the mobile station as part of the ranging process such that the mobile station performs a plurality of ranging processes within the sleep time interval.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.

Abstract: Wiring for a semiconductor device which is suitable for high density device packing, and a method for forming the same, are disclosed. The wiring includes: impurity regions formed in a substrate on both sides of an insulated gate electrode; a first conduction layer formed on the impurity regions; and a second conduction layer formed in contact with the first conduction layer on one side of the gate electrode. The method includes the steps of: forming impurity regions in a substrate on both sides of an insulated gate electrode; forming a first conduction layer on the impurity regions; and forming a second conduction layer in contact on one side of the gate electrode with the first conduction layer.

Abstract: The present invention relates to a device isolation structure and a device isolation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern.

Abstract: A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.

Abstract: Wiring for a semiconductor device which is suitable for high density device packing, and a method for forming the same, are disclosed. The wiring includes: impurity regions formed in a substrate on both sides of an insulated gate electrode; a first conduction layer formed on the impurity regions; and a second conduction layer formed in contact with the first conduction layer on one side of the gate electrode. The method includes the steps of: forming impurity regions in a substrate on both sides of an insulated gate electrode; forming a first conduction layer on the impurity regions; and forming a second conduction layer in contact on one side of the gate electrode with the first conduction layer.

Abstract: Wiring for a semiconductor device which is suitable for high density device packing, and a method for forming the same, are disclosed. The wiring includes: impurity regions formed in a substrate on both sides of an insulated gate electrode; a first conduction layer formed on the impurity regions; and a second conduction layer formed in contact with the first conduction layer on one side of the gate electrode. The method includes the steps of: forming impurity regions in a substrate on both sides of an insulated gate electrode; forming a first conduction layer on the impurity regions; and forming a second conduction layer in contact on one side of the gate electrode with the first conduction layer.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.

Abstract: A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.

Abstract: A method of fabricating a semiconductor device having a memory device region and a logic device region on a substrate includes the steps of forming first and second gate lines on the substrate at the memory device region and the logic device region, respectively, forming a sidewall insulating layer on both sides of each of the first and second gate lines, forming a plurality of impurity regions in the substrate, forming a silicon nitride layer on the memory device including the first gate lines, forming a silicide layer on the second gate line and impurity regions at the logic device region, and forming an oxide layer on an exposed surface excluding portions over each one of the impurity regions at the memory region and the logic device region, respectively.

Abstract: The present invention relates to a device isolation structure and a device solation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern.

Abstract: A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it.

Abstract: A fabrication method for a semiconductor memory device, which forms a capacitor over a bit line, includes the steps of forming an active region pattern on a semiconductor substrate, forming a field oxide region for electrically isolating single devices in the semiconductor substrate, forming a gate insulating film on the semiconductor substrate, forming a first conductive film to serve as a gate electrode on the gate insulating film, forming a first insulating film having a first etching characteristic on the first conductive film, and patterning the first insulating film and the first conductive film to form a plurality of word line patterns. Next a second insulating film, having the first etching characteristic, is formed over the semiconductor substrate, and is etched to form sidewall spacers at lateral walls of each word line pattern. A third insulating film is then formed over the semiconductor substrate, and removed from regions where a bit line is to be formed.

Abstract: A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.