Abstract: A method for forming metal line of a semiconductor device in which, if the aspect ratio of the contact holes is big, contact holes are buried with a CVD method using the HDP method, and the line process is simplified to improve the reliability is disclosed, including the steps of forming an insulating film having a contact hole on a semiconductor substrate; forming a barrier metal layer on the insulating film including the contact hole; and forming a metal line layer on the barrier metal layer with a CVD method using a high density plasma.

Abstract: A method for fabricating an integrated circuit includes the steps of forming an isolating insulation film on a portion of a semiconductor substrate, forming a gate insulating film, a first conductive layer, an insulating film and a second conductive layer successively on the semiconductor substrate including the isolating insulation film, selectively removing the second conductive layer and the insulating film to pattern an upper electrode of a capacitor in a capacitor forming region and a dummy gate electrode in a transistor forming region, respectively, forming a lower electrode mask in the capacitor forming region, and selectively removing the first conductive layer and the gate insulating film by using the lower electrode mask and the dummy gate electrode as masks, to form a lower electrode of the capacitor and the gate electrode of the transistor.

Abstract: A semiconductor device capacitor structure comprises a semiconductor substrate having an impurity diffusion region; an insulating layer formed on the semiconductor substrate and having a contact hole on the impurity diffusion region; a first lower electrode of a half ring type formed on the insulating film along an upper edge of the contact hole; a second lower electrode formed on a surface of the substrate exposed through the contact hole, a wall of the contact hole, and the first lower electrode; a dielectric layer formed on the first and second lower electrodes; and an upper electrode formed on the dielectric layer. This structure increases capacitance, thereby improving the characteristics and reliability of the device.

Abstract: A metal wiring for semiconductor devices having a double-layer passivation film structure consisting of an intermetallic compound layer formed on a copper thin film and made of a metal reacting with copper to form an intermetallic compound and a metal nitride layer formed over the intermetallic compound. This double-layer passivation film structure is obtained by depositing a metal layer, capable of reacting with copper to form an intermetallic compound, over the copper wiring, and annealing the metal layer in a nitrogen atmosphere, thereby forming an intermetallic compound layer over the copper wiring. By virtue of the double-layer passivation film structure, the copper wiring has a great improvement in the reliability. A metal silicide layer is formed between a diffusion region and a diffusion barrier layer in the contact hole of the semiconductor device. The diffusion barrier layer, which is formed on an insulating layer doped with nitrogen ions, is changed into a metal nitride film.

Abstract: A method of fabricating a CMOSFET includes the steps of selectively forming first and second conductive type wells in a semiconductor substrate, forming an isolation insulating layer at interface of the first and second conductive type wells, forming a first gate electrode formed of a first conductive type electrode over a predetermined area of the second conductive type well and a second gate electrode successively formed of a second conductive type electrode, a diffusion preventing layer, and the first conductive type electrode over a predetermined area of the first conductive type well, forming sidewall spacers on both sides of each of the first and second gate electrodes, forming second and first conductive type impurity regions under surfaces of the first and second conductive type wells, respectively, at both sides of the first and second gate electrodes and the their sidewall spacers, and forming a silicide layer on the first and second gate electrodes and on the semiconductor substrate where the first

Abstract: A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it.

Abstract: A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.

Abstract: A CMOS fabrication method includes the steps of providing a substrate having a surface, forming a first conductive well adjacent to the surface of the substrate, forming a second conductive well adjacent to the surface of the substrate, a portion of the first conductive well overlapping a portion of the second conductive well, forming a field oxide in the overlapping portion of the first and second conductive wells forming a first gate over the first conductive well and a second gate over the second conductive well, masking the first conductive well and implanting second conductive impurities on the second conductive well and masking the second conductive well and implanting first conductive impurities on the first conductive well.

Abstract: The present invention provides a process for forming an MOS semiconductor device having an LDD structure, which includes a forming a gate electrode by first etching a conductive layer to a certain depth by an RIE process and by second etching the conductive layer by an isotropic plasma etching process. In forming the source/drain of the device, an n.sup.+ source/drain and an n.sup.- source/drain are formed in a sequential manner. The gate line first is formed with its width over-sized compared with its channel length, and finally is formed to its final size.

Abstract: A semiconductor memory cell has a semiconductor substrate, an active region disposed on the semiconductor substrate and having two impurity regions, a gate electrode disposed on the active region, a field region isolated from the active region on the semiconductor substrate and having a contract hole, a capacitor disposed over the active region and field region on the semiconductor substrate, and a buried region disposed under the field region and the bit line contacting the first impurity region through the contact hole.

Abstract: A method for forming a contact between a conductive layer and a portion of the substrate during manufacture of a semiconductor device is disclosed. The process includes the steps of: (a) covering a semiconductor substrate with an insulating layer, and forming a contact hole on the portion where a contact is to be formed; (b) forming a metal layer on the whole surface of the substrate, and implanting positive ions into the metal layer; and (c) heat-treating the whole substrate so as to form a silicide layer. The metals used are those which can react with silicon to form a silicide, and may be selected from high melting point metals including Co, Ti, Ta, Ni, Mo, and Hf. The ions used are ions including H+ or halogen element ions, and a heat treatment is carried out so that the implanted positive ions may spread on/in the grain boundaries, or that the positive ions may bond with dangling bonds.

Abstract: A semiconductor fabrication apparatus which includes a collimator made of a net type heating material which generates Joule heating when electric power is supplied thereto. The apparatus includes a negative electrode having a metallic target, a positive electrode arranged opposite the negative electrode, on which positive electrode a semiconductor substrate is mounted, and the collimator being mounted between the negative electrode and the positive electrode and near the semiconductor substrate, with the collimator being made of a net type heating material and designed so that Joule heating is generated therein when a current is applied thereto.

Abstract: A semiconductor device capacitor structure comprises a semiconductor substrate having an impurity diffusion region; an insulating layer formed on the semiconductor substrate and having a contact hole on the impurity diffusion region; a first lower electrode of a half ring type formed on the insulating film along an upper edge of the contact hole; a second lower electrode formed on a surface of the substrate exposed through the contact hole, a wall of the contact hole, and the first lower electrode; a dielectric layer formed on the first and second lower electrodes; and an upper electrode formed on the dielectric layer. This structure increases capacitance, thereby improving the characteristics and reliability of the device.

Abstract: A method for forming a via contact of a semiconductor device includes the steps of forming a first insulating layer on a substrate, forming a lower conducting layer on the first insulating layer, forming a third insulating layer on the lower conducting layer, forming a first photoresist on the third insulating layer, etching the third insulating layer to form a via pillar, removing the first photoresist, forming a second photoresist on the via pillar and the lower conducting layer, etching the second photoresist except on the via pillar and a portion of the lower conducting layer, forming a metal line by removing portions of the lower conducting layer from which the second photoresist has been etched, removing the second photoresist that has not been etched, forming a second insulating layer on the metal line, the first insulating layer, and the via pillar, etching the second insulating layer to expose an upper surface of the via pillar, etching the via pillar to thereby form a via hole through the second ins

Abstract: A method for fabricating a capacitor of a semiconductor device, includes the steps of: forming a first insulating layer and then a second insulating layer on the first insulating layer; removing the second insulating layer of a first electrode region of a capacitor; forming a side wall at a side of the second insulating layer; etching the first insulating layer by using the side wall of the second insulating layer as a mask so as to form a contact hole; forming a first electrode of a capacitor on the side wall and on the contact hole; forming a dielectric layer on the first electrode of the capacitor; and forming a second electrode of the capacitor on the dielectric layer.

Abstract: A process for the isolation of a semiconductor layer on an insulator. A process for isolating a semiconductor layer on an insulator is disclosed that includes the steps of: forming a first insulating layer on a semiconductor substrate, and opening a window by etching the first insulating layer which becomes an epitaxial growth seed; depositing a semiconductor layer and growing an epitaxial layer which has the same crystal structure as the semiconductor substrate under the window; forming an active area of the epitaxial layer by a photolithographic process; forming a second insulating layer on and at the side of the active area and on the first insulating layer; and isolating an active area from the semiconductor layer by forming a third insulator layer in the window by an oxidation process.

Abstract: An improved device isolation method for a semiconductor device capable of independently and compatibly providing an isolation film in the interior of well and an isolation film between wells during a consistent process, so that latch-up characteristic can be improved even in a device requiring a design rule of below 0.5 .mu.m, which includes a first step which combines a second step which forms a device isolation film within a well and a third step which forms a device isolation film between wells, the second and third steps being compatible to each other during the same step.

Abstract: A semiconductor memory cell has a semiconductor substrate, an active region disposed on the semiconductor substrate and having two impurity regions, a gate electrode disposed on the active region, a field region isolated from the active region on the semiconductor substrate and having a contract hole, a capacitor disposed over the active region and field region on the semiconductor substrate, and a buried region disposed under the field region and the bit line contacting the first impurity region through the contact hole.

Abstract: An improved twin well formation method for a semiconductor device capable of improving the latch-up characteristic in DRAM device which requires a high integration density and of improving a recess problem which occurs due to the capacitor, which includes the steps of a first step which forms an insulation film on a semiconductor substrate having a first region and a second region; a second step which forms a first temporary film on an insulation film of the first region; a third step which forms a first side wall spacer at the first temporary side wall; a fourth step which implants a first conductive ion to a substrate of a second region; a fifth step which forms a second temporary film on a substrate of the second region; a sixth step which removes the first temporary film; a seventh step which implants a second conductive ion to a substrate of the first region; and an eighth step which anneals and removes the second temporary film and the first insulation spacer.

Abstract: A gate-drain overlapped device, comprising: a first conductive type substrate; a gate insulating film formed on the substrate; a gate comprising a gate conductive line patterned on the gate insulating film, and a conductive layer coated on the gate conductive line and extending to a predetermined length on the gate insulating film; and a drain/source region comprising a second conductive type low density diffusion region in the substrate below the extending area of the conductive layer and a second conductive type high density diffusion region in contact with the low density diffusion region in the substrate, which is significantly improved in the resistance of a polysilicon gate conductive line and in uniform electrical properties.