Abstract: An artificial intelligence calculation semiconductor device is provided. The artificial intelligence calculation semiconductor device comprising: a control unit; and a MAC (Multiply and Accumulator) calculator which executes a homomorphic encryption calculation through the control unit, wherein the MAC calculator includes an NTT (Numeric Theoretic Transform)/INTT (Inverse NTT) circuit which generates cipher texts by performing a homomorphic multiplication calculation through transformation or inverse transformation of data, a cipher text multiplier which executes a multiplication calculation between the cipher texts, a cipher text adder/subtractor which executes addition and/or subtraction calculations between the cipher texts, and a rotator which performs a cyclic shift of a slot of the cipher texts.

Abstract: A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.

Abstract: A signal processing method of a semiconductor device, the method including: receiving a first digital code of a first digital signal; generating a constraint vector; masking the first digital code with a transmitting mask based on the constraint vector; and outputting the masked first digital code and a Data Bus Inversion (DBI) bit of the mask.

Abstract: A data transmission method for transmitting a data signal using four data signal levels during a unit interval and transmitting a data bus inversion (DBI) signal using two DBI signal levels during the unit interval, the method including: receiving n (n is a natural number) data, each of the n data including a first bit and a second bit; counting the number of data in which the first bit and the second bit have the same value among the n data; in response to the counting result being less than or equal to a predetermined number, transmitting the n data using the four data signal levels, together with a DBI signal having a first DBI signal level; and in response to the counting result being greater than the predetermined number, transmitting data, which is obtained by changing a value of either of the first bit and the second bit of the n data, using the four data signal levels, together with a DBI signal having a second DBI signal level different from the first DBI signal level.

Abstract: A signal processing method of a semiconductor device, the method including: receiving a first digital code of a first digital signal; generating a constraint vector; masking the first digital code with a transmitting mask based on the constraint vector; and outputting the masked first digital code and a Data Bus Inversion (DBI) bit of the mask.

Abstract: Provided are a data receiving device and a corresponding method for receiving the data. The data receiving device comprises a path control logic configured to store L symbol paths, where L is a natural number equal to or greater than 2, L feedback filters configured to calculate L inter-symbol interferences (ISI) for the L symbol paths, respectively, L operators configured to remove the L inter-symbol interferences from an output of a feed-forward equalizer, and a path metric calculator configured to receive outputs of the L operators and calculate a path metric for each of the L symbol paths, wherein the path control logic is configured to select L values among the calculated path metrics for the L symbol paths to update the L symbol paths.

Abstract: A data transmission method for transmitting a data signal using four data signal levels during a unit interval and transmitting a data bus inversion (DBI) signal using two DBI signal levels during the unit interval, the method including: receiving n (n is a natural number) data, each of the n data including a first bit and a second bit; counting the number of data in which the first bit and the second bit have the same value among the n data; in response to the counting result being less than or equal to a predetermined number, transmitting the n data using the four data signal levels, together with a DBI signal having a first DBI signal level; and in response to the counting result being greater than the predetermined number, transmitting data, which is obtained by changing a value of either of the first bit and the second bit of the n data, using the four data signal levels, together with a DBI signal having a second DBI signal level different from the first DBI signal level.

Abstract: Provided are a data receiving device and a corresponding method for receiving the data. The data receiving device comprises a path control logic configured to store L symbol paths, where L is a natural number equal to or greater than 2, L feedback filters configured to calculate L inter-symbol interferences (ISI) for the L symbol paths, respectively, L operators configured to remove the L inter-symbol interferences from an output of a feed-forward equalizer, and a path metric calculator configured to receive outputs of the L operators and calculate a path metric for each of the L symbol paths, wherein the path control logic is configured to select L values among the calculated path metrics for the L symbol paths to update the L symbol paths.

Abstract: An artificial intelligence calculation semiconductor device is provided. The artificial intelligence calculation semiconductor device comprising: a control unit; and a MAC (Multiply and Accumulator) calculator which executes a homomorphic encryption calculation through the control unit, wherein the MAC calculator includes an NTT (Numeric Theoretic Transform)/INTT (Inverse NTT) circuit which generates cipher texts by performing a homomorphic multiplication calculation through transformation or inverse transformation of data, a cipher text multiplier which executes a multiplication calculation between the cipher texts, a cipher text adder/subtractor which executes addition and/or subtraction calculations between the cipher texts, and a rotator which performs a cyclic shift of a slot of the cipher texts.

Abstract: A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.

Abstract: An apparatus that receives a non-binary polar code through a channel includes a low-complexity decoder and a memory. The low-complexity decoder is configured to selectively calculate first common terms for input symbols in the non-binary polar code other than a first input symbol corresponding to a first target output symbol. The selective calculation uses a lower triangular kernel and log likelihood ratios of the input symbols generated based on a channel characteristic of the channel. The low-complexity decoder is also configured to calculate log likelihood ratios of the first target output symbol using the first common terms and to determine a value of the first target output symbol based on the log likelihood ratios of the first target output symbol. The memory is accessible by the low-complexity decoder and is configured to store the first common terms.

Abstract: An apparatus that receives a non-binary polar code through a channel includes a low-complexity decoder and a memory. The low-complexity decoder is configured to selectively calculate first common terms for input symbols in the non-binary polar code other than a first input symbol corresponding to a first target output symbol. The selective calculation uses a lower triangular kernel and log likelihood ratios of the input symbols generated based on a channel characteristic of the channel. The low-complexity decoder is also configured to calculate log likelihood ratios of the first target output symbol using the first common terms and to determine a value of the first target output symbol based on the log likelihood ratios of the first target output symbol.

Abstract: A storage device including: a memory controller configured to output user data received from outside of the storage device in a write operation mode and receive read data in a read operation mode; and a memory device including a memory cell array and a random input and output (I/O) engine, the random I/O engine configured to encode the user data provided from the memory controller using a random I/O code, in the write operation mode, and to generate the read data by decoding internal read data read by a data I/O circuit from the memory cell array using the random I/O code, in the read operation mode.

Abstract: A method of operating a memory system, having a non-volatile memory device, includes processing a response to a first request toward the memory device by using an original key, in response to the first request, generating and storing first parity data corresponding to the original key, and deleting the original key.

Abstract: A display device includes a display unit including pixels, a memory to store degradation data of the pixels, a group-setting portion to classify the pixels into degradation regions according to a degradation degree and based on the degradation data, perform a contour-simplifying process with respect to the degradation regions, classify the degradation regions into labeling regions according to proximity of adjacent ones of the degradation regions, and set one of the degradation regions as a reference region, a sensor to sense electric characteristics of the degradation regions and the reference region as they separately emit light, a compensation amount controller to compare the electric characteristics of the degradation regions with electric characteristics of the reference region, and calculate a per-position compensation data corresponding to a position of the labeling regions, and a converter to convert a first image data into a second image data based on the per-position compensation data.

Abstract: A controller for a display device includes an adjuster and a compensator. The adjuster adjusts at least one parameter of a modeling equation based on a measured current of a pixel. The modeling equation including the at least one adjusted parameter is indicative of a real time degree of degradation of the pixel. The compensator compensates for image data corresponding to emission of light from the pixel.

Abstract: Provided are methods for operating a non-volatile memory controller. A method for operating a non-volatile memory controller includes dividing data provided from a host into first unit data and second unit data, encoding the first unit data into first codewords including n number of bits (n is an integer equal to or more than 1), encoding the second unit data into second codewords including n-w number of bits (w is an integer less than n and equal to or more than 1) corresponding to a bit having a value of 0 among the n number of bits of the first codewords, performing bit-to-state mapping on the first codewords and the second codewords using a predetermined bitmap, and programming the first codewords and the second codewords to a first page and a second page of a non-volatile memory, respectively.

Abstract: A method is provided for operating a data storage device capable of compensating for an initial threshold voltage shift of multiple memory cells. The method includes generating a first compression value for a first write address corresponding to a first write request input during a first time interval among different time intervals, and storing the first compression value in a first table among multiple tables.

Abstract: Provided are a flash memory device, a flash memory system, and methods of operating the same. A method of operating a flash memory system includes selecting memory cells of a flash memory in response to an authentication challenge, programming pieces of input data into the selected memory cells, respectively, reading the selected memory cells and generating and storing control information, dividing the selected memory cells into at least one first region memory cell and at least one second region memory cell based on the control information, and setting read values of the at least one first region memory cell and the at least one second region memory cell as a first value and a second value, respectively, and generating an authentication response in the response to the authentication challenge.

Abstract: An organic light emitting display and a method for driving the organic light emitting display. The organic light emitting display includes a display unit, a data accumulator, and a data compensator. The display unit is configured to be driven by image data. The data accumulator is configured to compress and accumulate first data corresponding to a first portion of the image data for driving a first region of the display unit, identify a second region of the display unit from the first region by analyzing the accumulated first data, and compress and accumulate second data corresponding to a second portion of the image data for driving the second region with a compression ratio based on a size of the second region. The data compensator is configured to compensate the image data based on the accumulated first and second data.