Patents by Inventor Chang-Lin Yeh

Chang-Lin Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210193545
    Abstract: A semiconductor package includes a substrate having a first side and a second side opposite to the first side, a first type semiconductor die disposed on the first side of the substrate, a first compound attached to the first side and encapsulating the first type semiconductor die, and a second compound attached to the second side, causing a stress with respect to the first type semiconductor die in the first compound. A method for manufacturing the semiconductor package described herein is also disclosed.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 24, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Yu CHEN, Chang-Lin YEH, Ming-Hung CHEN
  • Patent number: 10991656
    Abstract: A semiconductor device package includes a first substrate, a second substrate disposed over the first substrate, and a surface mount device (SMD) component disposed between the first substrate and the second substrate. The SMD component includes a plurality of connection electrodes electrically connecting the first substrate to the second substrate, and the plurality of connection electrodes are electrically disconnected from each other.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 27, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Lin Yeh, Jen-Chieh Kao
  • Publication number: 20210118760
    Abstract: A semiconductor device package comprises a carrier, a stop layer, a barrier layer and an encapsulant. The carrier has a first surface and a second surface recessed with respect to the first surface. The stop layer is disposed on the second surface of the carrier. The barrier layer is disposed on the stop layer and protruded from the first surface of the carrier. The encapsulant is disposed on the first surface of the carrier. Further, the encapsulant has a side surface disposed on the barrier layer.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chang-Lin YEH
  • Publication number: 20210090982
    Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Lin YEH, Yu-Chang CHEN
  • Publication number: 20210076510
    Abstract: A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Yung I. YEH, Chang-Lin YEH, Sheng-Yu CHEN
  • Publication number: 20210066354
    Abstract: A semiconductor device package includes a main substrate, at least one thin film transistor (TFT) module, at least one first electronic component, at least one encapsulant and a plurality of light emitting devices. The main substrate has a first surface and a second surface opposite to the first surface. The thin film transistor (TFT) module is disposed adjacent to and electrically connected to the first surface of the main substrate. The first electronic component is disposed adjacent to and electrically connected to the first surface of the main substrate. The encapsulant covers the at least one thin film transistor (TFT) module and the at least one first electronic component. The light emitting devices are electrically connected to the at least one thin film transistor (TFT) module.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Yung I. YEH, Chang-Lin YEH, Sheng-Yu CHEN
  • Publication number: 20210057398
    Abstract: A semiconductor device package includes a first substrate, a dielectric layer, a thin film transistor (TFT) and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The dielectric layer is disposed on the first surface of the first substrate. The dielectric layer has a first surface facing away from the first substrate and a second surface opposite to the first surface. The TFT layer is disposed on the dielectric layer. The electronic component is disposed on the second surface of the first substrate. A roughness of the first surface of the dielectric layer is less than a roughness of the first surface of the first substrate.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Sheng-Yu CHEN, Chang-Lin YEH, Yung-I YEH
  • Publication number: 20210057572
    Abstract: A semiconductor device package includes a display device, an electronic module and a conductive adhesion layer. The display device includes a first substrate and a TFT layer. The first substrate has a first surface and a second surface opposite to the first surface. The TFT layer is disposed on the first surface of the first substrate. The electronic module includes a second substrate and an electronic component. The second substrate has a first surface facing the second surface of the first substrate and a second surface opposite to the first surface. The electronic component is disposed on the second surface of the second substrate. The conductive adhesion layer is disposed between the first substrate and the second substrate.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Sheng-Yu CHEN, Chang-Lin YEH, Yung-I YEH
  • Publication number: 20200402911
    Abstract: A semiconductor device package includes a first substrate, a second substrate disposed over the first substrate, and a surface mount device (SMD) component disposed between the first substrate and the second substrate. The SMD component includes a plurality of connection electrodes electrically connecting the first substrate to the second substrate, and the plurality of connection electrodes are electrically disconnected from each other.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Lin YEH, Jen-Chieh KAO
  • Publication number: 20200402897
    Abstract: A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chang-Lin YEH
  • Patent number: 10861779
    Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: December 8, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Lin Yeh, Yu-Chang Chen
  • Publication number: 20200312733
    Abstract: A semiconductor package structure includes a substrate having a first surface and a second surface opposite to the first surface; a first encapsulant disposed on the first surface of the substrate, and defining a cavity having a sidewall, wherein an accommodating space is defined by the sidewall of the cavity of the first encapsulant and the substrate, and the accommodating space has a volume capacity; and a connecting element disposed adjacent to the first surface of the substrate and in the cavity, wherein a volume of the connecting element is substantially equal to the volume capacity of the accommodating space.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Lin YEH, Jen-Chieh KAO, Sheng-Yu CHEN, Yu-Chang CHEN, Yu-Chang CHEN
  • Publication number: 20200234977
    Abstract: In one or more embodiments, a semiconductor package device includes a substrate, a trace, a structure, a barrier element and an underfill. The substrate has a first surface including a filling region surrounded by the trace. The structure is disposed over the filling region and electrically connected to the substrate. The barrier element is disposed on the trace. The underfill is disposed on the filling region.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 23, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chang-Lin YEH
  • Publication number: 20200161200
    Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yi CHEN, Chang-Lin YEH, Jen-Chieh KAO
  • Patent number: 10629454
    Abstract: In one or more embodiments, a semiconductor package device includes a substrate, a trace, a structure, a barrier element and an underfill. The substrate has a first surface including a filling region surrounded by the trace. The structure is disposed over the filling region and electrically connected to the substrate. The barrier element is disposed on the trace. The underfill is disposed on the filling region.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chang-Lin Yeh
  • Patent number: 10580713
    Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 3, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi Chen, Chang-Lin Yeh, Jen-Chieh Kao
  • Publication number: 20190393140
    Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.
    Type: Application
    Filed: February 5, 2019
    Publication date: December 26, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Lin YEH, Yu-Chang CHEN
  • Publication number: 20190393126
    Abstract: A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.
    Type: Application
    Filed: January 30, 2019
    Publication date: December 26, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shiu-Fang YEN, Chang-Lin YEH, Jen-Chieh KAO
  • Patent number: 10483254
    Abstract: An electronic module includes a first sub-module and a second sub-module. The first sub-module includes a first substrate, a first electronic component disposed on the first substrate and a first electrode. The second sub-module includes a second substrate, a second electronic component disposed on the second substrate and a second electrode spaced from the first electrode. The second electrode faces the first electrode to form a capacitor for transmitting an alternating current (AC) signal between the first sub-module and the second sub-module.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: November 19, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chang-Lin Yeh
  • Patent number: 10438889
    Abstract: The disclosure relates to an electronic module and a manufacturing method of the same. The electronic module includes a substrate, an electronic component, a first package body, a magnetic layer, a coil and a second package body. The electronic component is on the substrate. The first package body is on the substrate and covers the electronic component. The magnetic layer is on the first package body. The coil is on the magnetic layer. The coil includes a first section and a second section spaced from the first section. The first section and the second section are connected by a conductive material. The second package body is on the magnetic layer and covers the coil.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: October 8, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chang-Lin Yeh