Abstract: A semiconductor device package includes a substrate, a package body, a conductive layer, a dielectric layer, a magnetic layer, a first insulating layer and a coil. The package body is disposed on the substrate. The package body has a first part and a second part disposed above the first part. The conductive layer is disposed on the first part of the package body and is electrically connected to the substrate. The dielectric layer is disposed on the conductive layer. The magnetic layer is disposed on the dielectric layer. The first insulating layer is disposed on the magnetic layer. The coil is disposed on the first insulating layer. The coil has a first terminal electrically connected with the magnetic layer.

Abstract: A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first surface. The package body covers at least a portion of the surface of the substrate. The via is disposed in the package body and includes a conductive layer and a first intermediate layer. The conductive layer is electrically connected with the pad. The first intermediate layer is adjacent to the conductive layer. The interconnect is disposed on the first intermediate layer.

Abstract: A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element.

Abstract: In one or more embodiments, a semiconductor package device includes a substrate, a trace, a structure, a barrier element and an underfill. The substrate has a first surface including a filling region surrounded by the trace. The structure is disposed over the filling region and electrically connected to the substrate. The barrier element is disposed on the trace. The underfill is disposed on the filling region.

Abstract: A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element.

Abstract: A semiconductor package device includes a substrate, an electronic component disposed on the substrate, and a package body. The electronic component has a first surface adjacent to the substrate and a second surface opposite to the first surface. The second surface has at least five edges, and the package body encapsulates the electronic component and exposes the second surface of the electronic component.

Abstract: A semiconductor device package includes a substrate, a package body, a conductive layer, a dielectric layer, a magnetic layer, a first insulating layer and a coil. The package body is disposed on the substrate. The package body has a first part and a second part disposed above the first part. The conductive layer is disposed on the first part of the package body and is electrically connected to the substrate. The dielectric layer is disposed on the conductive layer. The magnetic layer is disposed on the dielectric layer. The first insulating layer is disposed on the magnetic layer. The coil is disposed on the first insulating layer. The coil has a first terminal electrically connected with the magnetic layer.

Abstract: A semiconductor package device includes a substrate, a first package body, a permeable element and a coil. The substrate includes a first surface. The first package body encapsulates the first surface of the substrate. The permeable element includes a first portion disposed on the first surface of the substrate and a second portion disposed on the package body. The coil is within the first package body.

Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.

Abstract: A semiconductor package device includes a substrate, a first package body, a permeable element and a coil. The substrate includes a first surface. The first package body encapsulates the first surface of the substrate. The permeable element includes a first portion disposed on the first surface of the substrate and a second portion disposed on the package body. The coil is within the first package body.

Abstract: An electronic module includes a first sub-module and a second sub-module. The first sub-module includes a first substrate, a first electronic component disposed on the first substrate and a first electrode. The second sub-module includes a second substrate, a second electronic component disposed on the second substrate and a second electrode spaced from the first electrode. The second electrode faces the first electrode to form a capacitor for transmitting an alternating current (AC) signal between the first sub-module and the second sub-module.

Abstract: The disclosure relates to an electronic module and a manufacturing method of the same. The electronic module includes a substrate, an electronic component, a first package body, a magnetic layer, a coil and a second package body. The electronic component is on the substrate. The first package body is on the substrate and covers the electronic component. The magnetic layer is on the first package body. The coil is on the magnetic layer. The coil includes a first section and a second section spaced from the first section. The first section and the second section are connected by a conductive material. The second package body is on the magnetic layer and covers the coil.

Abstract: A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first surface. The package body covers at least a portion of the surface of the substrate. The via is disposed in the package body and includes a conductive layer and a first intermediate layer. The conductive layer is electrically connected with the pad. The first intermediate layer is adjacent to the conductive layer. The interconnect is disposed on the first intermediate layer.

Abstract: A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.

Abstract: A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.

Abstract: A bonding strength test device suits to perform a bonding strength test for at least one solder ball that fixed on a substrate. The bonding strength test device includes a fixed base and an impact apparatus. The impact apparatus has a first end and a second end corresponding to the first end. While an impact is applied to the first end of the impact apparatus, the impact apparatus moves downward, and the second end of the impact apparatus hits the solder ball on the substrate for performing the bonding strength test. Besides, the fixed base is used for limiting the downward movement of the impact apparatus.

Abstract: A semiconductor package structure includes a substrate, a first chip, a second chip, a wire, and an encapsulant. The substrate with a cavity has a first surface and a second surface. The cavity penetrates the first surface and the second surface. The first surface and the second surface have a first solder pad and a second solder pad respectively. The first chip having a first active surface and a first non-active surface is disposed inside the cavity. The first active surface has a first contact pad. The second chip having a second active surface and a second non-active surface is disposed on the second surface. The second non-active surface is adhered to the first non-active surface. The second active surface has a second contact pad. The wire is used for electrically connecting the second contact pad and the second solder pad. The encapsulant disposed on the substrate fills the cavity.

Abstract: A bonding strength test device suits to perform a bonding strength test for at least one solder ball that fixed on a substrate. The bonding strength test device includes a fixed base and an impact apparatus. The impact apparatus has a first end and a second end corresponding to the first end. While an impact is applied to the first end of the impact apparatus, the impact apparatus moves downward, and the second end of the impact apparatus hits the solder ball on the substrate for performing the bonding strength test. Besides, the fixed base is used for limiting the downward movement of the impact apparatus.

Abstract: A chip package includes a package substrate, a chip and a molding compound. The package substrate has a carrying surface and a back surface opposite to the carrying surface. The chip is mounted on the carrying surface and electrically connected to the package substrate. Furthermore, the molding compound is applied over the carrying surface to cover the chip and a part of the package substrate. The outline of a juncture between the molding compound and the package substrate is a smooth closed curve so that thermal stress is uniformly distributed over the juncture to prevent stress concentration. The reliability of the package structure is thereby improved.