Patents by Inventor Chang Liu

Chang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11180483
    Abstract: Amine substituted reverse pyrimidine compounds and forms thereof that inhibit the function and reduce the level of B-cell specific Moloney murine leukemia virus integration site 1 (Bmi-1) protein and methods for their use to inhibit Bmi-1 function and reduce the level of Bmi-1 to treat a cancer mediated by Bmi-1 are described herein.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 23, 2021
    Assignee: PTC Therapeutics, Inc.
    Inventors: Chang-Sun Lee, Ramil Baiazitov, Liangxian Cao, Thomas W. Davis, Wu Du, Ronggang Liu, Young-Choon Moon, Steven D. Paget, Hongyu Ren, Nadiya Sydorenko, Richard Gerald Wilde
  • Patent number: 11183439
    Abstract: A package structure for power devices includes a heat dissipation insulating substrate, a plurality of power devices, a heat dissipation baseplate, and a thermal interface layer. The heat dissipation insulating substrate has a first surface and a second surface which are opposite to each other, and the power devices are coupled to the first surface of the heat dissipation insulating substrate. The heat dissipation baseplate is disposed at the second surface of the heat dissipation insulating substrate, wherein at least one of a surface of the heat dissipation baseplate and the second surface of the heat dissipation insulating substrate has at least one plateau, and the plateau is at least disposed within a projected area of the plurality of power devices. The thermal interface layer is disposed between the second surface of the heat dissipation insulating substrate and the surface of the heat dissipation baseplate.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 23, 2021
    Assignee: ACTRON TECHNOLOGY CORPORATION
    Inventors: Hsin-Chang Tsai, Ching-Wen Liu
  • Patent number: 11181669
    Abstract: An optical system is provided and includes a fixed assembly, a movable element and a driving module. The fixed assembly has a main axis. The movable element is movable relative to the fixed assembly and has a surface facing a first optical element. The driving module is configured to drive the movable element to move relative to the fixed assembly.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 23, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Che-Wei Chang, Chih-Wen Chiang, Chen-Er Hsu, Fu-Yuan Wu, Shou-Jen Liu, Chih-Wei Weng, Mao-Kuo Hsu, Hsueh-Ju Lu, Che-Hsiang Chiu
  • Publication number: 20210357952
    Abstract: Introduced here are approaches for identifying the optimal send time for messages by accounting for hidden confounders, such as the content of those messages, delivery channel, etc. These approaches use a causal inference framework to discover and then remove the impact of hidden confounders. These approaches may be employed by a marketing and analytics platform (or simply “marketing platform”) that may be used to design, implement, or review digital marketing campaigns. The marketing platform can consider the send time as a treatment and then employ machine learning (ML) models that consider the send time, features of the recipient, and hidden confounders to produce a ranked series of send times with the effect of the hidden confounders marginalized. Approaches to performing offline evaluations that mimic A/B tests using data related to existing field experiments are also introduced here.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Xinyue Liu, Suofei Wu, Chang Liu, Jun He, Zhenyu Yan, Wuyang Dai, Shengyun Peng
  • Publication number: 20210358863
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 18, 2021
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu
  • Publication number: 20210354862
    Abstract: The present invention is a pallet strapping device having a platform, a lower guiding strap portion, an upper guiding strap portion, a first frame portion, a second frame portion and a central guiding strap portion. By controlling a first guiding strap portion, a second guiding strap portion, and the central guiding strap portion that is moved to a retracted position, a first guiding strap circulation path can be formed. In addition, by controlling the first frame portion, the second frame portion and the central guiding strap portion that is moved to an extended position, a second guiding strap circulation path is formed. The present invention is capable of switching to different strapping paths corresponding to different pallets for strapping. Besides, it is quite convenient to conduct strapping tasks under the condition that the corresponding pallets is not needed to depart from the platform of the pallet strapping device.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 18, 2021
    Inventors: CHIN-CHANG LIU, CHI-JAN SU
  • Publication number: 20210359003
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect disposed within a dielectric structure over a substrate. A memory device includes a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the lower interconnect. A sidewall spacer includes an interior sidewall that continuously extends from along an outermost sidewall of the top electrode to below an outermost sidewall of the bottom electrode. The sidewall spacer further includes an outermost sidewall that extends from a bottom surface of the sidewall spacer to above a top of the bottom electrode.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 18, 2021
    Inventors: Yuan-Tai Tseng, Chung-Chiang Min, Shih-Chang Liu
  • Publication number: 20210357744
    Abstract: Providing a task-aware recommendation of hyperparameter configurations for a neural network architecture. First, a joint space of tasks and hyperparameter configurations are constructed using a plurality of tasks (each of which corresponds to a dataset) and a plurality of hyperparameter configurations. The joint space is used as training data to train and optimize a performance prediction network, such that for a given unseen task corresponding to one of the plurality of tasks and a given hyperparameter configuration corresponding to one of the plurality of hyperparameter configurations, the performance prediction network is configured to predict performance that is to be achieved for the unseen task using the hyperparameter configuration.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 18, 2021
    Inventors: Gaurav MITTAL, Victor Manuel FRAGOSO ROJAS, Nikolaos KARIANAKIS, Mei CHEN, Chang LIU
  • Patent number: 11177211
    Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
  • Patent number: 11177188
    Abstract: A chip packaging structure includes a heat dissipation substrate, a pre-molded chipset, an interconnection and a second encapsulant. The pre-molded chipset is located on the heat dissipation substrate. The interconnection is located in the packaging structure and electrically connects the heat dissipation substrate and the pre-molded chipset. The second encapsulant covers part of the heat dissipation substrate, part or all of the interconnection, and part or all of the pre-molded chipset. The pre-molded chipset includes a thermally conductive substrate, at least two chips, a patterned circuit, and a first encapsulant. The patterned circuit is located in the pre-molded chipset. At least two chips are electrically connected by the patterned circuit. The first encapsulant covers at least two chips and part or all of the patterned circuit. A manufacturing method of a chip packaging structure is also provided.
    Type: Grant
    Filed: September 13, 2020
    Date of Patent: November 16, 2021
    Assignee: ACTRON TECHNOLOGY CORPORATION
    Inventors: Hsin-Chang Tsai, Ching-Wen Liu
  • Patent number: 11172884
    Abstract: The present disclosure relates to intelligent wearable devices, and provides a method and a module for detecting a wearing state, and a wearable device thereof. The method for detecting a wearing state is applied to the wearable device, and the wearable device includes a light emitter and a light receiver. The detection method includes: controlling the light emitter to emit at least two types of light signals to a user; controlling the light receiver to receive reflected light corresponding to the at least two types of light signals reflected by the user; and determining the wearing state of the wearable device according to change trends of at least two types of the received reflected light. The wearing state of the wearable device is determined more accurately by adopting embodiments of the present disclosure.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 16, 2021
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Hongliang Duan, Wangwang Yang, Songrong Bai, Chang Liu, Zhiyao Liu
  • Patent number: 11177525
    Abstract: The present disclosure provides a battery pack for a hybrid vehicle. The battery pack includes: multiple battery cells, a housing, a first end plate, a second end plate, a bearing plate and an upper cover, wherein the housing is provided with a bottom portion and side walls extending from the periphery of the bottom portion and forming an upper portion opening; the housing is configured for accommodating the multiple battery cells and the two end plates, when the multiple battery cells are sequentially arranged and mounted into the housing, the first end plate and the second end plate are located at two end sides of the sequentially arranged multiple battery cells to laterally fix the multiple battery cells; the bearing plate is mounted above the top portions of the multiple battery cells; and the upper cover is mounted above the housing to cover the upper portion opening of the housing.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: November 16, 2021
    Assignee: CPS Technology Holdings LLC
    Inventors: Binbin Fan, Liang Cheng, Wei Qu, Peng Song, Yingyao Fu, Chang Liu, Jason D. Fuhr, Martin Wiegmann, Xugang Zhang, Jennifer L. Czarnecki
  • Publication number: 20210352829
    Abstract: A cover for covering an opening of a socket formed by a housing comprises a body; one or more bosses extending from the body, a first locking mechanism, a second locking mechanism, and a release tab. The bosses movably couple the body to the housing such that the body is movable between first and second positions. The first locking mechanism releasably attaches to the housing to secure the body in the first position. The second locking mechanism releasably attaches to the housing to secure the body in the second position. The release tab aids in detaching the first locking mechanism from the first wall and the second locking mechanism from the second wall. When the body is in the first position, the body allows access to the socket through the opening. When the body is in the second position, the body prevents access to the socket through the opening.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 11, 2021
    Inventors: Chun CHANG, Hsin-Chieh LIN, Chih-Hao CHANG, Yi-Fu LIU
  • Publication number: 20210351085
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Inventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
  • Publication number: 20210352818
    Abstract: A release mechanism is disclosed that can facilitate safely and efficiently removing an expansion card from a computing device. The release mechanism can be installed on a motherboard around an expansion slot, and can include an opening that permits access to the expansion slot to allow an expansion card to be installed therein. When removal of the expansion card is desired, a handled of the release mechanism can be pulled, causing contact surfaces of the release mechanism to push the expansion card away from the expansion slot with even force, removing the need to tilt the expansion card.
    Type: Application
    Filed: August 4, 2020
    Publication date: November 11, 2021
    Inventors: Chun CHANG, Hsin-Chieh LIN, Chih-Hao CHANG, Yi-Fu LIU
  • Publication number: 20210351348
    Abstract: A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 11, 2021
    Inventors: Chern-Yow Hsu, Chung-Chiang Min, Shih-Chang Liu
  • Patent number: 11169118
    Abstract: The present invention discloses a method for extending the detection range of a structural health monitoring (SHM) system. A structure being monitored is scanned multiple times. A scan with no collection delay covers an original detection area of the SHM system. Scans with collection delays cover extended detection areas. The SHM system's detection range is extended when results of multiple scans with different collection delays are combined.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: November 9, 2021
    Inventors: Chang Zhang, Lei Liu
  • Patent number: 11171147
    Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu
  • Publication number: 20210340870
    Abstract: An automatic coal mining machine and a fluidized coal mining method are provided. A first excavation cabin is configured to cut coal seam to obtain raw coal and to be transported to a first coal preparation cabin for separating coal blocks from gangue. Then, the obtained coal blocks are transported to a first fluidized conversion reaction cabin. The first fluidized conversion reaction cabin converts the energy form of the coal block into liquid, gas or electric energy, which is transported to a first energy storage cabin for storing. Coal mining and conversion are carried out in underground coal mines, so it is not necessary to raise coal blocks to the ground for washing and conversion, thereby reducing the transportation cost of coal, improving the utilization degree of coal, and avoiding the pollution of the ground environment caused by waste in the mining and conversion process.
    Type: Application
    Filed: March 23, 2018
    Publication date: November 4, 2021
    Applicants: CHINA UNIVERSITY OF MINING AND TECHNOLOGY, BEIJING, SHENZHEN UNIVERSITY
    Inventors: Yang JU, Heping XIE, Yong ZHANG, Yan ZHU, Feng GAO, Xiaodong NIE, Changbing WAN, Jinxin SONG, Chang LU, Hongbin LIU, Zhangyu REN
  • Publication number: 20210343485
    Abstract: A method of preparing a soft carbon material for high-voltage supercapacitors includes: providing an initial soft carbon material characterized by: (A) a first carbon layer spacing greater than 0.345 nm but less than 0.360 nm; (B) a crystal plane (002) with a length (Lc) less than 6 nm; (C) a crystal plane (101) with a length (La) less than 6 nm; and (D) an intensity ratio (I(002)/I(101)) of the crystal plane (002) to the crystal plane (101) obtained by XRD analysis being less than 60; performing an alkaline activation on the initial soft carbon material with an alkaline activator to obtain a first processing carbon material; and performing an electrochemical activation on the first processing carbon material with an electrolyte to obtain the soft carbon material for the high-voltage supercapacitors.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 4, 2021
    Inventors: YAN-SHI CHEN, GAO-SHEE LEU, YU-CHIEN LIU, CHI-CHANG HU