Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

Abstract: The present disclosure relates to a split gate memory device. In some embodiments, the split gate memory device includes a memory gate arranged over a substrate, and a select gate arranged over the substrate. An inter-gate dielectric layer is arranged between sidewalls of the memory gate and the select gate that face one another. The inter-gate dielectric layer extends under the memory gate. A first dielectric is disposed above the inter-gate dielectric layer and is arranged between the sidewalls of the memory gate and the select gate.

Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate electrode is an L-shaped structure, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: The present disclosure relates to a flash memory cell. In some embodiments, the flash memory cell has a control gate arranged over a substrate, and a select gate separated from the substrate by a gate dielectric layer. A charge trapping layer has a first portion disposed between the select gate and the control gate, and a second portion arranged under the control gate. A first control gate spacer is arranged on the second portion of the charge trapping layer. A second control gate spacer is arranged on the second portion of the charge trapping layer and is separated from the control gate by the first control gate spacer.

Abstract: The present disclosure relates to an integrated circuits device having a RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect layer surrounded by a lower ILD layer and a bottom electrode disposed over the lower metal interconnect layer. The bottom electrode has a lower portion surrounded by a bottom dielectric layer and an upper portion wider than the lower portion. The bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer. The integrated circuit device also has a RRAM dielectric with a variable resistance located on the bottom electrode, and a top electrode located over the RRAM dielectric. The integrated circuit device also has a top dielectric layer located over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.

Abstract: The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region. A first plurality of dielectric bodies are formed within the first plurality of openings and a second plurality of dielectric bodies are formed within the second plurality of openings. A second masking layer is formed over the first masking layer and the first and second plurality of dielectric bodies. The first and second masking layers are removed at the memory cell region, and a first conductive layer is formed to fill recesses between the first plurality of dielectric bodies. A planarization process reduces a height of the first conductive layer and removes the first conductive layer from over the boundary region.

Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.

Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Abstract: A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including floating gates and control gates over the floating gates. A common gate layer is formed over the gate stacks and the semiconductor substrate, and lining sidewalls of the gate stacks. A first etch is performed into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to form an erase gate between the gate stacks. Hard masks are respectively formed over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer. A second etch is performed into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate.

Abstract: A method of fabricating MEMS device includes forming a plurality of rounded edge trenches on a sacrificial layer over a carrier substrate. Then, formation of a polycrystalline silicon layer over the sacrificial layer to fill the trenches. A plurality of stoppers is defined by the trenches and protrudes from the polycrystalline silicon layer toward the carrier substrate Subsequently, a portion of the sacrificial layer is removed to define a recess between the polycrystalline silicon layer and a carrier substrate and expose the stoppers.

Abstract: The present disclosure relates to a flash memory device, and associated methods. In some embodiments, the flash memory device has a gate stack with a control gate separated from a floating gate by a control gate dielectric. An erase gate disposed on a first side of the gate stack. A word line is disposed on a second side of the gate stack that is opposite the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. The shape of the word line optimizes the contact resistance of the word line and allows for an overlying cap spacer formed on the word line to be well defined, which can provide more reliable read/write operations and/or better performance.

Abstract: A method of manufacturing a split gate flash memory cell is provided. A select gate is formed on a semiconductor substrate. A sacrificial spacer is formed laterally adjacent to the select gate and on a first side of the select gate. A charge trapping layer is formed lining upper surfaces of the select gate and the sacrificial spacer, and further lining a sidewall surface of the select gate on a second side of the select gate that is opposite the first side of the select gate. A memory gate is formed over the charge trapping layer and on the second side of the select gate. The sacrificial spacer is removed. The resulting semiconductor structure is also provided.

Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: A split-gate flash memory cell for improved erase speed is provided. An erase gate and a floating gate are laterally spaced over a semiconductor substrate. The floating gate has a height increasing towards the erase gate, a concave sidewall surface neighboring the erase gate, and a tip defined an interface of the concave sidewall surface and an upper surface of the floating gate. A control gate and a sidewall spacer are arranged over the upper surface of the floating gate. The control gate is laterally offset from the tip of the floating gate, and the sidewall spacer is laterally arranged between the control gate and the tip. A method for manufacturing the split-gate flash memory cell is also provided.

Abstract: An integrated circuit (IC) device is provided. The IC device includes a first substrate having a frontside and a backside. The backside includes a first cavity extending into the first substrate. A dielectric layer is disposed on the backside of the first substrate, and includes an opening corresponding to the first cavity and a trench extending laterally away from the opening and terminating at a gas inlet recess. A recess in the frontside of the first substrate extends downwardly from the frontside to the dielectric layer. The recess has substantially vertical upper sidewalls which adjoin lower sidewalls which taper inwardly from the substantially vertical sidewalls to points on the dielectric layer which circumscribe the gas inlet recess. A conformal sealant layer is arranged over the frontside of the first substrate, along the substantially vertical upper sidewalls, and along the lower sidewalls. The sealant layer hermetically seals the gas inlet recess.

Abstract: A semiconductor device includes a substrate, at least one logic device and a split gate memory device. The at least one logic device is located on the substrate. The split gate memory device is located on the substrate and comprises a memory gate and a select gate. The memory gate and the select gate are adjacent to and electrically isolated with each other. A top of the select gate is higher than a top of the memory gate.

Abstract: A method of fabricating MEMS device includes forming a plurality of rounded edge trenches on a sacrificial layer over a carrier substrate. Then, formation of a polycrystalline silicon layer over the sacrificial layer to fill the trenches. A plurality of stoppers is defined by the trenches and protrudes from the polycrystalline silicon layer toward the carrier substrate Subsequently, a portion of the sacrificial layer is removed to define a recess between the polycrystalline silicon layer and a carrier substrate and expose the stoppers.

Abstract: The present disclosure relates to a split gate memory device which requires less number of processing steps than traditional baseline processes and methods of making the same. Word gate/select gate (SG) pairs are formed around a sacrificial spacer. The resulting SG structure has a distinguishable non-planar top surface. The spacer layer that covers the select gate also follows the shape of the SG top surface. A dielectric disposed above the inter-gate dielectric layer and arranged between the neighboring sidewalls of the each memory gate and select gate provides isolation between them.