Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.

Abstract: Some embodiments relate to a memory device with an asymmetric floating gate geometry. A control gate is arranged over a floating gate. An erase gate is arranged laterally adjacent the floating gate, and is separated from the floating gate by a tunneling dielectric layer. A sidewall spacer is arranged along a vertical sidewall of the control gate, and over an upper surface of the floating gate. A portion of the floating gate upper surface forms a “ledge,” or a sharp corner, which extends horizontally past the sidewall spacer. A sidewall of the floating gate forms a concave surface, which tapers down from the ledge towards a neck region within the floating gate. The ledge provides a faster path for tunneling of the electrons through the tunneling dielectric layer compared to a floating gate with a planar sidewall surface. The ledge consequently improves the erase speed of the memory device.

Abstract: Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.

Abstract: A phase change memory (PCM) cell with a heating element electrically isolated from laterally surrounding regions of the PCM cell by a cavity is provided. A dielectric region is arranged between first and second conductors. A heating plug is arranged within a hole extending through the dielectric region to the first conductor. The heating plug includes a heating element running along sidewalls of the hole, and includes a sidewall structure including a cavity arranged between the heating element and the sidewalls. A phase change element is in thermal communication with the heating plug and arranged between the heating plug and the second conductor. Also provide is a method for manufacturing the PCM cell.

Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

Abstract: A method of manufacturing a semiconductor structure of a pair of split gate flash memory cells is provided. A pair of select gates spaced on a semiconductor substrate is formed, and a sacrificial spacer filling a central region between the select gates is formed. A charge trapping dielectric layer is formed conformally along sidewalls of the select gates and over top surfaces of the sacrificial spacer and the select gates, and a pair of memory gates corresponding to the pair of select gates is formed over and laterally abutting the charge trapping dielectric layer. The resulting semiconductor structure is also provided.

Abstract: Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed over an upper surface of the control gate, and a composite spacer is disposed on a source-facing sidewall surface of the control gate. The capping structure and the composite spacer prevent damage to the control gate during one more etch processes used for contact formation to the memory device. To further limit or prevent the select gate sidewall etching, some embodiments provide for an additional liner oxide layer disposed along the drain-facing sidewall surface of the select gate. The liner oxide layer is configured as an etch stop layer to prevent etching of the select gate during the one or more etch processes. As a result, the one or more etch processes leave the control gate and select gate substantially intact.

Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have flat upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.

Abstract: A split gate flash memory cell device with a line-shaped charge trapping dielectric structure is provided. A semiconductor substrate includes a first source/drain region and a second source/drain region. A select gate and a memory gate are spaced over the semiconductor substrate between the first and second source/drain regions. A line-shaped charge trapping dielectric structure is arranged between the semiconductor substrate and the memory gate. A method for manufacturing the split gate flash memory cell device is also provided.

Abstract: A method of manufacturing a semiconductor structure of a pair of split gate flash memory cells is provided. A pair of select gates spaced on a semiconductor substrate is formed, and a sacrificial spacer filling a central region between the select gates is formed. A charge trapping dielectric layer is formed conformally along sidewalls of the select gates and over top surfaces of the sacrificial spacer and the select gates, and a pair of memory gates corresponding to the pair of select gates is formed over and laterally abutting the charge trapping dielectric layer. The resulting semiconductor structure is also provided.

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided.

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate located over the semiconductor substrate between the source and drain regions. The floating gate is arranged between the word line and the erase gate. Even more, the semiconductor structure includes a dielectric disposed between the erase and floating gates. A thickness of the dielectric between the erase and floating gates is variable and increases towards the semiconductor substrate. A method of manufacturing the semiconductor structure is also provided.

Abstract: A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device.

Abstract: Some embodiments of the present disclosure relate to a memory device, which includes a floating gate formed over a channel region of a substrate, and a control gate formed over the floating gate. First and second spacers are formed along sidewalls of the control gate, and extend over outer edges of the floating gate to form a non-uniform overhang, which can induce a wide distribution of erase speeds of the memory device. To improve the erase speed distribution, an etching process is performed on the first and second spacers prior to erase gate formation. The etching process removes the overhang of the first and second spacers at an interface between a bottom region of the first and second spacers and a top region of the floating gate to form a planar surface at the interface, and improves the erase speed distribution of the memory device.

Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

Abstract: Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.