Patents by Inventor Chang Rong Wu
Chang Rong Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9070871Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.Type: GrantFiled: October 31, 2014Date of Patent: June 30, 2015Assignee: NANYA TECHNOLOGY CORP.Inventors: Chun-I Hsieh, Chang-Rong Wu
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Patent number: 8999733Abstract: An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.Type: GrantFiled: October 28, 2014Date of Patent: April 7, 2015Assignee: Nanya Technology Corp.Inventors: Chun-I Hsieh, Chang-Rong Wu, Neng-Tai Shih
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Publication number: 20150064805Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.Type: ApplicationFiled: October 31, 2014Publication date: March 5, 2015Inventors: Chun-I Hsieh, Chang-Rong Wu
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Publication number: 20150044852Abstract: An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventors: Chun-I Hsieh, Chang-Rong Wu, Neng-Tai Shih
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Patent number: 8916392Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.Type: GrantFiled: May 27, 2013Date of Patent: December 23, 2014Assignee: Nanya Technology Corp.Inventors: Chun-I Hsieh, Chang-Rong Wu
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Patent number: 8901527Abstract: An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.Type: GrantFiled: July 2, 2010Date of Patent: December 2, 2014Assignee: Nanya Technology Corp.Inventors: Chun-I Hsieh, Chang-Rong Wu, Neng-Tai Shih
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Publication number: 20130252348Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.Type: ApplicationFiled: May 27, 2013Publication date: September 26, 2013Applicant: NANYA TECHNOLOGY CORP.Inventors: Chun-I Hsieh, Chang-Rong Wu
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Patent number: 8535954Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.Type: GrantFiled: February 22, 2012Date of Patent: September 17, 2013Assignee: Nanya Technology Corp.Inventors: Chun-I Hsieh, Chang-Rong Wu
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Patent number: 8487290Abstract: A method for fabricating an RRAM is provided. First, a bottom electrode is formed. A resistive layer is formed on the bottom electrode. A top electrode is then formed on the resistive layer, wherein the top electrode is selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). Finally, the top electrode is irradiated with UV light.Type: GrantFiled: November 27, 2008Date of Patent: July 16, 2013Assignee: Nanya Technology Corp.Inventors: Chun-I Hsieh, Chang-Rong Wu, Neng-Tai Shih, Kou-Chen Liu
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Publication number: 20130075812Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.Type: ApplicationFiled: September 22, 2011Publication date: March 28, 2013Inventors: Hsin-Jung Ho, Jeng-Ping Lin, Neng-Tai Shih, Chang-Rong Wu, Chiang-Hung Lin, Chih-Huang Wu
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Patent number: 8395209Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.Type: GrantFiled: September 22, 2011Date of Patent: March 12, 2013Assignee: Nanya Technology Corp.Inventors: Hsin-Jung Ho, Jeng-Ping Lin, Neng-Tai Shih, Chang-Rong Wu, Chiang-Hung Lin, Chih-Huang Wu
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Patent number: 8395139Abstract: A memory structure includes an active area surrounded by first isolation trenches and second isolation trenches; a bit line trench recessed into the active area of the semiconductor substrate; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench. The bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions. A bit line is embedded in the bit line trench. A word line is embedded in the word line trench. A vertical transistor is built in each of the pillar-shaped sub-regions. A resistive memory element is electrically coupled to the vertical transistor.Type: GrantFiled: December 6, 2011Date of Patent: March 12, 2013Assignee: Nanya Technology Corp.Inventors: Hsin-Jung Ho, Chang-Rong Wu, Wei-Chia Chen
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Publication number: 20120146168Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.Type: ApplicationFiled: February 22, 2012Publication date: June 14, 2012Inventors: Chun-I Hsieh, Chang-Rong Wu
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Patent number: 8149614Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.Type: GrantFiled: March 31, 2010Date of Patent: April 3, 2012Assignee: Nanya Technology Corp.Inventors: Chun-I Hsieh, Chang-Rong Wu
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Publication number: 20120001141Abstract: An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.Type: ApplicationFiled: July 2, 2010Publication date: January 5, 2012Inventors: Chun-I Hsieh, Chang-Rong Wu, Neng-Tai Shih
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Patent number: 8089060Abstract: A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed on the surface; and an ion conductor disposed among the anode, the cathode and the specific structure, wherein the specific structure is one of a bulging area on the surface of the cathode and an insulating layer with an opening.Type: GrantFiled: July 22, 2009Date of Patent: January 3, 2012Assignee: Nanya Technology Corp.Inventors: Chun-I Hsieh, Shih-Shu Tsai, Chang-Rong Wu
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Publication number: 20110241138Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Inventors: Chun-I Hsieh, Chang-Rong Wu
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Patent number: 7943917Abstract: A non-volatile memory cell and the fabrication method thereof are provided. The non-volatile memory cell comprises a top electrode, a bottom electrode and an oxide layer disposed between the top electrode and the bottom electrode. The oxide layer comprises a relatively low oxygen content layer adjacent to the bottom electrode, a relatively high oxygen content layer adjacent to the top electrode, and a transition layer disposed between the relatively high and the relatively low oxygen content layers. The transition layer has an oxygen concentration within a range between those of the relatively high and the relatively low oxygen content layers.Type: GrantFiled: April 8, 2009Date of Patent: May 17, 2011Assignee: Nanya Technology Corp.Inventors: Chun-I Hsieh, Chang-Rong Wu
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Publication number: 20110084248Abstract: Cross point memory arrays with CBRAM and RRAM stacks are presented. A cross point memory array includes a first group of substantially parallel conductive lines and a second group of substantially parallel conductive lines, oriented substantially perpendicular to the first group of substantially parallel conductive lines. An array of memory stack is located at the intersections of the first group of substantially parallel conductive lines and the second group of substantially parallel conductive lines, wherein each memory stack comprises a conductive bridge memory element in series with a resistive-switching memory element.Type: ApplicationFiled: October 13, 2009Publication date: April 14, 2011Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Chun-I Hsieh, Chang-Rong Wu
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Publication number: 20100193762Abstract: A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed on the surface; and an ion conductor disposed among the anode, the cathode and the specific structure, wherein the specific structure is one of a bulging area on the surface of the cathode and an insulating layer with an opening.Type: ApplicationFiled: July 22, 2009Publication date: August 5, 2010Applicant: NANYA TECHNOLOGY CORP.Inventors: Chun-I Hsieh, Shih-Shu Tsai, Chang-Rong Wu