Abstract: A method of forming an interlayer dielectric (ILD) layer. A dielectric layer containing boron and phosphorous is formed overlying a substrate. A plasma treatment is subsequently performed on the dielectric layer using argon or nitrogen as a process gas. A capping layer is formed in-situ overlying the dielectric layer to serve as the ILD layer with the dielectric layer. A reflow process is subsequently performed on the ILD layer. A method for preventing formation of etching defects in a contact is also disclosed.

Abstract: The present invention provides a method for manufacturing a stacked-gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a titanium layer, and a WNX layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.

Abstract: A method for forming a deep trench capacitor buried plate. A substrate having a pad oxide and a pad nitride is provided. A deep trench is formed in the substrate. A doped silicate film is deposited on a sidewall of the deep trench. A sacrificial layer is deposited in the deep trench, and etched back to expose parts of the doped silicate film. Then, an etching process is performed to remove the exposed doped silicate film and parts of the pad oxide for forming a recess. The sacrificial layer is removed. A silicon nitride layer is deposited to fill the recess and to cover the doped silicate film. Finally, a thermal oxidation process is performed to form a doped ion region. The silicon nitride layer is removed. The doped silicate film is removed.

Abstract: A method of forming an interlayer dielectric (ILD) layer. A dielectric layer containing boron and phosphorous is formed overlying a substrate. A plasma treatment is subsequently performed on the dielectric layer using argon or nitrogen as a process gas. A capping layer is formed in-situ overlying the dielectric layer to serve as the ILD layer with the dielectric layer. A reflow process is subsequently performed on the ILD layer. A method for preventing formation of etching defects in a contact is also disclosed.

Abstract: A method of reducing trench aspect ratio. A trench is formed in a substrate. Using HDP-CVD, a conformal first oxide layer is formed on a surface of the trench. A conformal first nitride layer is formed on the first oxide layer. Part of the first nitride layer is removed to cause the first nitride layer to be lower than a top surface of the substrate. Using a BOE solution, the first nitride layer and part of the first oxide layer are removed to leave a remaining first oxide layer on the lower portion of the surface of the trench. Thus, the trench aspect ratio is reduced.

Abstract: A manufacturing method of a high aspect ratio shallow trench isolation region. A substrate with a trench therein is provided and placed into a chamber. A first insulation layer is formed on the substrate as well as inside the trench by high density plasma chemical vapor deposition. The majority of the first insulation layer outside the trench is removed by in situ etching using carbon fluoride as an etching gas with high selectivity for SiO2/SiN etching ratio, and a second insulation layer is formed on the first insulation layer by high density plasma chemical vapor deposition, filling the trench. According to the present invention, a high aspect ratio shallow trench isolation region without voids can thus be achieved.

Abstract: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

Abstract: A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.

Abstract: A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

Abstract: The invention provides a method for forming a bottle-shaped trench. A semiconductor substrate having a trench and a pad stack layer formed thereon is provided. A masking layer is then formed in the lower portion of the trench. Plasma nitridation is then performed to form a nitride layer covering the sidewalls of the trench, followed by removing the masking layer to expose the sidewalls of the trench. The lower portion of the trench is then expanded by etching to form a bottle-shaped trench.

Abstract: A memory device with vertical transistors and deep trench capacitors. This device includes a substrate containing at least one deep trench and a trench capacitor disposed in the bottom of the deep trench. A conducting wire is disposed on the trench capacitor. A trench top insulating layer, containing a first insulating layer and a second insulating layer surrounded by the first insulating layer, is disposed on the conducting wire. A control gate is disposed on the trench top insulating layer. A buried strap is provided in the substrate beside the conducting wire. A doping area is provided in the substrate beside the control gate. A manufacturing method for forming such memory device is also disclosed.

Abstract: A manufacturing method for a shallow trench isolation region with high aspect ratio. The method comprises the steps of providing a substrate with a trench therein, forming a first insulation layer on the substrate and inside the trench by high density plasma chemical vapor deposition (HDPCVD), removing the majority of the first insulation layer outside the trench by spray type etching, and forming a second insulation layer on the first insulation layer by low pressure CVD to fill the trench. According to the present invention, a void-free shallow trench isolation with high aspect ration can be achieved.

Abstract: A method of forming a high aspect ratio shallow trench isolation in a semiconductor substrate. The method includes the steps of forming a hard mask layer with a certain pattern on the semiconductor substrate, etching a portion of the semiconductor substrate not covered by the hard mask layer to form a high aspect ratio shallow trench in the semiconductor substrate; forming an oxide liner on the bottom and sidewall of the high aspect ratio shallow trench; performing a LPCVD to form a first oxide layer to fill the high aspect ratio shallow trench, a void being formed in the first oxide layer; etching a portion of the first oxide layer to a certain depth of the high aspect ratio shallow trench and to expose the void; and performing a HDPCVD to form a second oxide layer to fill the high aspect ratio shallow trench.

Abstract: A method for increasing the capacitance of deep trench capacitors. The method includes providing a substrate, forming a pad structure on the substrate, forming a photoresist defining the region of the deep trench on the pad structure, forming a deep trench in the substrate, removing the photoresist, forming a capacitor in the lower portion of the deep trench, forming a first insulation layer on the capacitor, forming an epitaxy layer on the sidewall of the deep trench above the first insulation layer as a liner to narrow the dimension of the deep trench, and removing the first insulation layer uncovered by the epitaxy layer.

Abstract: A method for making a bit line contact on a substrate is provided. Two gate conductor stacks are formed on a main surface of the substrate in close proximity to each other. A bit line contact forming area is defined above the area between the two gate conductor stacks. A silicon dioxide lining film is deposited on a top surface and sidewalls of the gate conductor stacks. A sacrificing layer is deposited on the silicon dioxide lining film. The sacrificing layer is then polished to expose the top surface of the gate conductor stacks. A spin-on-glass (SOG) film is then coated on the sacrificing layer. A resist pattern masking the bit line contact forming area is formed on the SOG film. The un-masked SOG film, sacrificing layer and silicon dioxide lining film are etched away. A silicon nitride thin film is deposited on the remaining SOG film. A BPSG layer is deposited on the silicon nitride thin film and is then polished to expose the SOG layer.

Abstract: A method of reducing trench aspect ratio. A trench is formed in a substrate. A conformal Si-rich oxide layer is formed on the surface of the trench by HDPCVD. A conformal first oxide layer is formed on the Si-rich oxide layer by HDPCVD. A conformal second oxide layer is formed on the first oxide layer by LPCVD. Part of the Si-rich oxide layer, the second oxide layer and the first oxide layer are removed by anisotropic etching to form an oxide spacer composed of a remaining Si-rich oxide layer, a remaining second oxide layer and a remaining first oxide layer. The remaining second oxide layer, part of the remaining first oxide layer and part of the Si-rich oxide layer are removed by BOE. Thus, parts of the remaining first and Si-rich oxide layers are formed on the lower surface of the trench, thereby reducing the trench aspect ratio.

Abstract: A method for increasing the capacitance of deep trench capacitors. The method includes providing a substrate, forming a pad structure on the substrate, forming a photoresist defining the region of the deep trench on the pad structure, forming a deep trench in the substrate, removing the photoresist, forming a capacitor in the lower portion of the deep trench, forming a first insulation layer on the capacitor, forming an epitaxy layer on the sidewall of the deep trench above the first insulation layer as a liner to narrow the dimension of the deep trench, and removing the first insulation layer uncovered by the epitaxy layer.

Abstract: A method of reducing trench aspect ratio. A trench is formed in a substrate. Using HDP-CVD, a conformal first oxide layer is formed on a surface of the trench. A conformal first nitride layer is formed on the first oxide layer. Part of the first nitride layer is removed to cause the first nitride layer to be lower than a top surface of the substrate. Using a BOE solution, the first nitride layer and part of the first oxide layer are removed to leave a remaining first oxide layer on the lower portion of the surface of the trench. Thus, the trench aspect ratio is reduced.

Abstract: A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench by spin-spraying to cover the oxide layer in the trench. An etchant is then sprayed over the surface of the semiconductor substrate to remove the uncovered oxide layer and expose the surface of the semiconductor substrate. The density of the etchant is less than that of the liquid etching shield. A second oxide layer is deposited in the trench to form isolation without voids or seams.

Abstract: A method for forming a trench isolation structure. First, a substrate having at least one trench is provided. The trench is filled with a spin on glass (SOG) layer. Subsequently, a baking is performed on the SOG layer. The SOG layer is etched back to a predetermined depth. Next, a curing is performed on the remaining SOG layer. Finally, an insulating layer is formed on the remaining SOG layer to fill the trench completely.