Patents by Inventor Chang Sup Ryu

Chang Sup Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100175915
    Abstract: The invention relates to a printed circuit board and a method of manufacturing the printed circuit board, in which the printed circuit board includes an insulating layer, a circuit layer embedded in the insulating layer and having a connection pad that is embedded in the insulating layer such that one side of the connection pad is flush with a surface of the insulating layer, and insulating materials configured to protect the circuit layer from an external environment and having an opening through which the connection pad is exposed. The invention makes the printed circuit board slim, and increases reliability and the degree of design freedom.
    Type: Application
    Filed: March 27, 2009
    Publication date: July 15, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jee Soo Mok, Je Gwang Yoo, Chang Sup Ryu
  • Patent number: 7707715
    Abstract: Disclosed is a method of fabricating a multilayer printed circuit board, which enables the formation of a micro circuit able to be realized through a semi-additive process using the CTE and rigidity of a metal carrier on a thin substrate which is difficult to convey.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electro-Mechanics, Co., Ltd.
    Inventors: Shuhichi Okabe, Je Gwang Yoo, Chang Sup Ryu, Myung Sam Kang, Jung Hyun Park, Ji Hong Jo, Jin Yong An, Soon Oh Jung
  • Publication number: 20100024212
    Abstract: A method of fabricating a multilayer printed circuit board, which enables the formation of a micro circuit able to be realized through a semi-additive process using the CTE and rigidity of a metal carrier on a thin substrate which is difficult to convey.
    Type: Application
    Filed: October 8, 2009
    Publication date: February 4, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD
    Inventors: Shuhichi Okabe, Je Gwang Yoo, Chang Sup Ryu, Myung Sam Kang, Jung Hyun Park, Ji Hong Jo, Jin Yong An, Soon Oh Jung
  • Publication number: 20100025092
    Abstract: A core substrate using paste bumps, the core substrate including a first paste bump board having a plurality of first paste bumps joined to a surface thereof; a second paste bump board having a plurality of second paste bumps facing the first paste bumps joined thereto; and an insulation element placed between the first paste bump board and the second paste bump board. In the core substrate, the first paste bumps and the second paste bumps are electrically interconnected.
    Type: Application
    Filed: October 6, 2009
    Publication date: February 4, 2010
    Applicant: Samsung Electro Mechanics Co., Ltd.
    Inventors: Yoong Oh, Chang-Sup Ryu, Dong-Jin Park, Jee-Soo Mok, Byung-Bae Seo
  • Publication number: 20100022052
    Abstract: A manufacturing method of a package on package with a cavity. The method can include forming a first upper substrate cavity in one side of an upper substrate; mounting an upper semiconductor chip on the other side of the upper substrate; forming a lower substrate cavity in one side of a lower substrate; mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate; and stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. The package on package and a manufacturing method thereof can reduce the overall thickness of the package by forming cavities in both upper and lower substrates to accommodate a semiconductor chip mounted in the lower substrate.
    Type: Application
    Filed: September 9, 2009
    Publication date: January 28, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jee-Soo Mok, Chang-Sup Ryu, Dong-Jin Park
  • Publication number: 20090308650
    Abstract: The printed circuit board is manufactured using a simple process of forming a bump on a first metal layer using fireable paste containing carbon nanotubes, firing the first metal layer including the bump, forming an insulating layer and a second metal layer on the first metal layer, and patterning the first and second metal layers, thus specific resistance of the resulting printed circuit board is decreased, and electrical conductivity and cooling performance are improved.
    Type: Application
    Filed: August 4, 2008
    Publication date: December 17, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Eung Suek Lee, Je Gwang Yoo, Chang Sup Ryu, Jun Oh Hwang, Jun Heyoung Park, Jee Soo Mok
  • Publication number: 20090301767
    Abstract: Disclosed is a printed circuit board including bumps formed using a conductive paste including carbon nanotubes and a photosensitive binder. A method of manufacturing the printed circuit board is also provided. The printed circuit board includes bumps formed using the conductive paste having carbon nanotubes, and can realize good electrical connection with electronic parts mounted thereon. The bumps can be formed at a fine pitch, thus realizing a circuit layer having a high density.
    Type: Application
    Filed: August 4, 2008
    Publication date: December 10, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jee Soo Mok, Je Gwang Yoo, Eung Suek Lee, Chang Sup Ryu
  • Publication number: 20090294739
    Abstract: The invention provides a conductive paste including a carbon nanotube and a printed circuit board using the same. The invention provides the conductive paste which exhibits an excellent electrical conductivity and allows the implementation of the X-Y interconnection and simultaneously the Z-interconnection without loosing the carbon nanotube's own original characteristics.
    Type: Application
    Filed: November 3, 2008
    Publication date: December 3, 2009
    Inventors: Eung-Suek Lee, Je-Gwang Yoo, Chang-Sup Ryu, Jun-Oh Hwang, Tae-Eun Chang, Jee-Soo Mok
  • Publication number: 20090294956
    Abstract: Disclosed herein is a cooling fin, which is excellent in cooling performance and is simply manufactured, a package substrate comprising the cooling fin, and a manufacturing method thereof. Fireable paste containing a carbon component is applied into grooves of a mold, thus forming a cooling fin having a pattern corresponding to the grooves. Thus, it enables the production of cooling fins having various configurations, thus improving a cooling performance of a package substrate incorporating the cooling fin.
    Type: Application
    Filed: July 22, 2008
    Publication date: December 3, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO. LTD.
    Inventors: Eung Suek Lee, Je Gwang Yoo, Chang Sup Ryu, Jun Oh Hwang, Jun Heyoung Park, Jee Soo Mok
  • Publication number: 20090294164
    Abstract: Disclosed herein is a printed circuit board including a landless via and a method of manufacturing the printed circuit board. The printed circuit board includes a landless via having no upper land. The via includes a circuit pattern having a line width smaller than the minimum diameter of the via. The via does not have an upper land on an end surface thereof having the minimum diameter, and thus a circuit pattern connected to the via is finely formed, resulting in the high-density circuit pattern. Thus, a compact printed circuit board having a reduced number of layers is realized.
    Type: Application
    Filed: July 15, 2008
    Publication date: December 3, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Han Kim, Je Gwang Yoo, Chang Sup Ryu, Chang Gun Oh
  • Patent number: 7622329
    Abstract: A core substrate and multilayer printed circuit board using paste bumps and manufacturing method thereof are disclosed. With the method of manufacturing a core substrate using paste bumps comprising: (a) aligning a pair of paste bump boards, each of which has a plurality of paste bumps joined to its surface, such that the paste bumps face each other, and (b) pressing the pair of paste bump boards together, where an insulation element is placed between the pair of paste bump boards, it is easier to implement interlayer electrical interconnection between circuit patterns, the thickness of the core substrate can readily be adjusted by adjusting the thickness of the insulation layer, the stiffness is improved as a pair of paste bump boards are pressed from the top and bottom, and high-density wiring can be formed more easily as the paste bumps are connected in pairs so that the diameters of the paste bumps formed on the paste bump boards can be reduced.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: November 24, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yoong Oh, Chang-Sup Ryu, Dong-Jin Park, Jee-Soo Mok, Byung-Bae Seo
  • Patent number: 7605459
    Abstract: An aspect of the present invention features a manufacturing method of a package on package with a cavity. The method can comprise (a) forming a first upper substrate cavity in one side of an upper substrate; (b) mounting an upper semiconductor chip on the other side of the upper substrate; (c) forming a lower substrate cavity in one side of a lower substrate; (d) mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate; and (e) stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. The package on package and a manufacturing method thereof can reduce the overall thickness of the package by forming cavities in both upper and lower substrates to accommodate a semiconductor chip mounted in the lower substrate.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: October 20, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jee-Soo Mok, Chang-Sup Ryu, Dong-Jin Park
  • Publication number: 20090250259
    Abstract: Disclosed herein is a multilayered printed circuit board, including: a build-up layer including a plurality of insulating layers and a plurality of circuit layers; an insulating resin layer, including bumps, formed on the outermost circuit layer of one side of the build-up layer; and a solder resist layer formed on the outermost layer of the other side of the build-up layer. The multilayered printed circuit board is manufactured by sequentially placing a build-up layer and a solder resist layer on one side of an insulating resin layer, the other side of which is provided with bumps. The present invention is advantageous in that the thickness of the multilayered printed circuit board is decreased, the production processes thereof is simplified, and the production efficiency is increased.
    Type: Application
    Filed: July 3, 2008
    Publication date: October 8, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jee Soo Mok, Je Gwang Yoo, Chang Sup Ryu
  • Publication number: 20090236131
    Abstract: Disclosed herein is a multilayered circuit board, including: a multilayered printed circuit board manufactured using the method includes an insulating resin layer having via holes, on one side of which a first circuit layer including circuit patterns is formed, and on the other side of which a second circuit layer, including connecting pads, is formed, the pads protruding over the via holes; a build-up layer formed on the first circuit layer, the build-up layer including a plurality of insulating layers and a plurality of circuit layers; and a solder resist layer formed on an outermost layer of the build-up layer.
    Type: Application
    Filed: July 31, 2008
    Publication date: September 24, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jee Soo Mok, Je Gwang Yoo, Chang Sup Ryu
  • Publication number: 20090236130
    Abstract: Disclosed herein is a multilayered circuit board, including: a metal base layer including a metal layer formed through-holes, an insulating film formed on a surface of the metal layer, a first circuit layer having circuit patterns formed on one side of the metal layer and a second circuit layer having protruding connecting pads, formed on the other side of the metal layer; a build-up layer formed on the first circuit layer; and a solder resist layer. The multilayered printed circuit board is advantageous in that the thickness thereof is decreased and the bending strength and radiation characteristics thereof are improved.
    Type: Application
    Filed: July 3, 2008
    Publication date: September 24, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jee Soo Mok, Je Gwang Yoo, Chang Sup Ryu
  • Patent number: 7592708
    Abstract: With a semiconductor package according to an aspect of the present invention comprising a board having circuit lines, solder resist formed on a surface of the board, and a chip mounted on the board and having at least one bump attached to at least a portion of the circuit lines, where the solder resist comprises a perimeter groove, which exposes at least a portion of the circuit lines, and an extension groove, which is connected to the perimeter groove, and where encapsulant is filled in the perimeter groove and the extension groove, the filling characteristics of the encapsulant is improved for greater reliability in the electrical connections between the chip and the board.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: September 22, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung-Gu Kim, Je-Gwang Yoo, Yong-Bin Lee, Yoo-Keum Wee, Seok-Hwan Huh, Chang-Sup Ryu
  • Publication number: 20090229875
    Abstract: A printed circuit board having a fine pattern and related manufacturing method that includes providing a carrier plate; coating the carrier plate with a photosensitive material; forming a first circuit pattern on the photosensitive material; forming a first circuit layer by drying a conductive paste printed into a space between the photosensitive materials where the first circuit pattern is formed; depositing an insulation layer on the first circuit layer; processing via holes penetrating the insulation layer; coating the insulation layer with the photosensitive material and then forming a second circuit pattern in the photosensitive material; forming a second circuit layer and filling the via holes by drying the conductive paste printed into a space between the photosensitive materials, where the second circuit pattern is formed, and the via holes; and removing the carrier plate.
    Type: Application
    Filed: May 20, 2009
    Publication date: September 17, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jee-Soo Mok, Chang-Sup Ryu, Eung-Suek Lee, Ki-Hwan Kim, Sung-Yong Kim
  • Patent number: 7583512
    Abstract: Disclosed is a PCB including an embedded passive component and a method of fabricating the same. The PCB includes at least two circuit layers in which circuit patterns are formed. At least one insulating layer is interposed between the circuit layers. A pair of terminals is vertically formed through the insulating layers, plated with a first conductive material, and separated from each other by a predetermined distance. The embedded passive component is interposed between the terminals and has electrodes formed on both sides thereof. The electrodes are separated from the terminals by a predetermined distance and electrically connected to the terminals through a second conductive material.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: September 1, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chang Sup Ryu, Myung Sam Kang
  • Publication number: 20090206468
    Abstract: A method of manufacturing a board on chip package including laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; removing the dry film; laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; mounting a semiconductor chip on the solder ball pad by a flip chip bonding; molding the semiconductor chip with a passivation material; removing the carrier film and the thin metal film; and laminating a lower photo solder resist under the solder ball pad. The board on chip package provides a high density circuit since a circuit pattern is formed using a seed layer.
    Type: Application
    Filed: April 3, 2009
    Publication date: August 20, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Myung-Sam Kang, Chang-Sup Ryu, Jung-Hyun Park, Hoe-Ku Jung, Ji-Eun Kim
  • Publication number: 20090184420
    Abstract: A post bump and a method of forming the post bump are disclosed. The method of forming the post bump can include: forming a resist layer, in which an aperture is formed in correspondence to a position of an electrode pad, over a substrate, on which the electrode pad is formed; forming a metal post by filling a part of the aperture with a metallic material; filling a remaining part of the aperture with solder; reflowing the solder by applying heat; and removing the resist layer. This method can be utilized to prevent deviations in the plated solder and prevent the unnecessary flowing of the solder over the sides of the metal post during reflowing, so that the amount of solder used can be minimized.
    Type: Application
    Filed: June 19, 2008
    Publication date: July 23, 2009
    Applicant: SAMSUNG ELECTROMECHANICS CO., LTD.
    Inventors: Jin-Won Choi, Chang-Sup Ryu, Seung-Hyun Cho, Seung-Wan Kim