Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.

Abstract: A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: Exhaust systems are described. In examples, an exhaust flow path couples exhaust ports with one or more turbochargers of an engine. The exhaust flow path may have a portion flowing through a cylinder head (e.g., couplable to the exhaust ports) and a portion flowing through an exhaust manifold (couplable to the cylinder head and the turbocharger(s)). The flow paths may be shaped to reduce the sharpness of turns between the exhaust ports and the turbocharger(s). For example, curves along the flow path may be less than 90 degrees or have a minimum curve radius, which may vary along the flow path. Additionally, at least two, independent flow paths may exist between the exhaust ports and the turbocharger(s). The cross-sectional shape of any part of the flow path may be elliptical, including at inlets and outlets.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: A self-moving device, including: a moving module, a task execution module, a control module. The control module is electrically connected to the moving module and the task execution module, controls the moving module to actuate the self-moving device to move, controls the task execution module to execute a working task. The self-moving device further includes a satellite navigation apparatus, electrically connected to the control module and configured to receive a satellite signal and output current location information of the self-moving device. The control module determines whether quality of location information output by the satellite navigation apparatus at a current location satisfies a preset condition, controls, if the quality does not satisfy the preset condition, the moving module to actuate the self-moving device to change a moving manner, to enable quality of location information output by the satellite navigation apparatus at a location after the movement to satisfy the preset condition.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Abstract: An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.

Abstract: A display panel, comprising a first insulating structural layer, a first crack detection line, a second insulating structural layer and a second crack detection line which are sequentially arranged on a substrate, wherein the first crack detection line and the second crack detection line are both located in a peripheral area and are arranged around a display area, one end of the first crack detection line is configured to receive a detection signal, and the other end of the first crack detection line is configured to output a first output signal, and one end of the second crack detection line is configured to receive a detection signal and the other end of the second crack detection line is configured to output a second output signal.

Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer.

Abstract: Disclosed are a method and a system for forecasting an agricultural product price based on signal decomposition and deep learning. The method includes: S1, obtaining price subsequences by performing a complementary ensemble empirical mode decomposition (CEEMD) on an original price sequence of agricultural products; S2, obtaining a reconstructed sequence based on the price subsequences; S3, obtaining data features of the reconstructed sequence based on the reconstructed sequence; and S4, constructing a Bi-directional Sequence to Sequence (BiSeq2seq) model, and inputting the data features of the reconstructed sequence into a CCS-Bi-directional Sequence to Sequence (CCS-BiSeq2seq) model to obtain a forecasting result.

Abstract: An imaging lens assembly module includes an imaging lens element set, a lens carrier and a light blocking structure. The imaging lens element set has an optical axis. At least one lens element of the lens elements is disposed in the lens carrier. The light blocking structure includes a light blocking opening. The optical axis passes through the light blocking opening, and the light blocking opening includes at least two arc portions and a shrinking portion. Each of the arc portions has a first curvature radius for defining a maximum diameter of the light blocking opening. The shrinking portion is connected to the arc portions for forming the light blocking opening into a non-circular shape. The shrinking portion includes at least one protruding arc which extends and shrinks gradually from the shrinking portion to the optical axis, and the protruding arc has a second curvature radius.

Abstract: A semiconductor device may include a source line, a bit line, and a gate structure located between the source line and the bit line. The gate structure may include conductive layers and insulating layers that are alternately stacked. The semiconductor device may include a topological insulator that may extend from the bit line to the source line through the gate structure. The topological insulator may include a non-conductor region and semiconductor regions coupled to the non-conductor region and located at a sidewall of the topological insulator. The semiconductor device may also include a memory layer surrounding the topological insulator.

Abstract: A CMOS device, and a method of manufacturing the same, includes a semiconductor substrate and a trench formed in the semiconductor substrate. The CMOS device also includes an oxide semiconductor layer disposed in the trench, the oxide semiconductor layer including a source region, a drain region, and a channel region between the source region and the drain region. The CMOS device further includes a buffer layer between the oxide semiconductor layer and the semiconductor substrate, a gate insulating layer on the oxide semiconductor layer, a gate electrode disposed on the gate insulating layer over the channel region of the oxide semiconductor layer, and impurities distributed in each of the source region and the drain region of the oxide semiconductor layer.

Abstract: An LED display device includes a system board, and multiple daughterboards that are assembled on the system board. The system board includes a drive power circuit, a first gate circuit and a second gate circuit. Each daughterboard includes a substrate, multiple LEDs that are disposed on the substrate, multiple first transistor switches that are respectively connected to the LEDs, and at least one second transistor switch that is connected to the LEDs. With respect to each daughterboard, the first transistor switches and the at least one second transistor switch cooperatively control current flows through the LEDs; the first transistor switches are further connected to the drive power circuit to respectively receive multiple drive currents, and are further connected to the first gate circuit to receive a timing signal; and the at least one second transistor switch is further connected to the second gate circuit to receive a timing signal.

Abstract: A light emitting display device includes a substrate, a drive power circuit, a gate circuit unit, multiple LEDs and a power switch unit. The power switch unit includes multiple first transistor switches and at least one second transistor switch that cooperatively control current flows through the LEDs. The first transistor switches are respectively connected to first terminals of the LEDs. The at least one second transistor switch is connected to second terminals of the LEDs. The first transistor switches are further connected to the drive power circuit to receive multiple drive currents, and are further connected to the gate circuit unit to receive a timing input. The at least one second transistor switch is further connected to the gate circuit unit to receive a timing input. The light emitting display device can have reduced parasitic capacitance effect, and thus reduced power consumption and have improved display quality.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. The methods can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC); performing a thermal simulation for each respective template of the IC based on a sequence of power patterns of tiles of the respective template; and training a neural network with a plurality of training data collected via thermal simulations performed for the templates of the IC. These systems and methods can use a machine learning predictor, that has been trained to determine a transient temperature rise across an entire IC, and then append the determined transient temperature rise to a system level thermal profile of the IC.

Abstract: The present disclosure provides a memory controller including a state detector detecting whether the memory device is in an idle state, a program controller, based on detection information that indicates a state of the memory device, selecting neighboring strings that are adjacent to a string that is coupled to a memory cell, among the memory cells, on which a program operation or a read operation was performed before the detecting, selecting monitoring memory cells that are coupled to at least one word line, the memory cells being a part of the neighboring strings, and controlling the memory device to perform a plurality of loops to program the monitoring memory cells, and a bad block selector selecting a memory block with the monitoring memory cells as a bad block based on a rate of increase in threshold voltage of a threshold voltage distribution of the monitoring memory cells.