Abstract: The invention refers to a diffusion plate and a backlight module having the diffusion plate. The diffusion plate comprises a plate-body and a plurality of pyramid-like structures arranged on a surface of the plate-body. Each pyramid-like structure has a bottom surface, a first convex portion and a second convex portion. The first convex portion and the second convex portion have different vertex angles, and therefore the pyramid-like structure can also be called as “pyramid-like structure with multiple vertex angles”. The pyramid-like structures with multiple vertex angles can increase the light splitting points, which can improve the light splitting effect of the diffusion plate. The light source of a single light-emitting diode can be divided into eight point-light sources (light splitting points) or more, which is double the number of light splitting points compared with the traditional pyramid structure with single vertex, and thus can greatly improve the light diffusion effect.

Abstract: The present disclosure provides a memory controller including a state detector detecting whether the memory device is in an idle state, a program controller selecting neighboring strings that are adjacent to a string that is coupled to a memory cell, among the memory cells, on which a program operation or a read operation is performed based on detection information that indicates a state of the memory device, selecting monitoring memory cells that are coupled to at least one word line, the memory cells being a part of the neighboring strings, and controlling the memory device to perform a plurality of loops to program the monitoring memory cells, and a bad block selector selecting a memory block with the monitoring memory cells as a bad block based on a rate of increase of a threshold voltage distribution of the monitoring memory cells.

Abstract: A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.

Abstract: A power supply device includes a casing, a battery module, and a cover. The casing has an accommodation space. The battery module is located in the accommodation space and includes a bottom frame, a plurality of battery units, and a top frame. The bottom frame is fixed to the casing, and the battery units are located between and fixed in position by the bottom frame and the top frame. The cover is mounted on the casing and covers the accommodation space.

Abstract: A battery module with an ability of homogenizing temperatures includes at least one battery pack and at least one temperature homogenizing element. The at least one battery pack includes a plurality of batteries. The plurality of the batteries are divided into a middle group of the batteries and an outer group of the batteries. The outer group of the batteries surround the middle group of the batteries. The at least one temperature homogenizing element is mounted around the middle group of the batteries. The at least one temperature homogenizing element has a plurality of fixing holes. The middle group of the batteries are inserted into the plurality of the fixing holes, and the outer group of the batteries are attached to an outer surface of an outer wall of the at least one temperature homogenizing element.

Abstract: There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a plurality of memory blocks each including a plurality of select transistors and a plurality of memory cells; a peripheral circuit for performing a general operation including a program operation, a read operation, and an erase operation on the plurality of memory blocks; and a control logic for controlling the peripheral circuit to operate in a heating mode in which the peripheral circuit applies heat to the plurality of memory blocks.

Abstract: A device for targeted repair of micro-nano damage of an inner ring of an aeroengine bearing by an electric-magnetic composite field includes a driving device, an ultrasonic shot peening device, a pulsed current generator and a magnet yoke-coil device. The driving device includes a motor and a rotating shaft. The motor drives the rotating shaft to drive a bearing inner ring to synchronously rotate. The ultrasonic shot peening device includes an ultrasonic shot peening cavity, an ultrasonic probe and steel balls, the ultrasonic probe extends into the cavity from an opening in a lower end of the cavity, and the steel balls are placed on the ultrasonic probe. An opening in an upper end of the cavity is placed below the bearing inner ring. The pulsed current generator generates pulsed current on the bearing inner ring. The magnet yoke-coil device can excite a magnetic field around the bearing inner ring.

Abstract: An electrical connection module and a power supply integration structure of a connection interface of the electrical connection module are disclosed. The electrical connection module includes a connection body and a terminal structure. The connection body has a jack communicating with the inside of the connection body for installing the terminal structure in the connection body to communicate with the jack. The terminal structure includes multiple terminals arranged in two rows. Each row has one or more power terminals. The power terminal in one row is defined as a positive pin, the power terminal of the other row is defined as a negative pin. An end of the power terminal in each row is electrically connected to a conductive part respectively. The electrical connection module is disposed across a power guide base, and the conductive part is in contact with the power guide base to for the power integration.

Abstract: A controller including a test manager configured to output a program command for performing a program operation of a memory block and a suspend command for stopping the program operation, and a memory interface configured to transmit the program command to a memory device including the memory block, and transmit the suspend command to the memory device after a set time elapses. The test manager outputs a read command for reading memory cells included in the memory block, the memory interface calculates a count value by counting data output from the memory device in response to the read command, and the test manager generates status information on the memory block according to the count value.

Abstract: A semiconductor memory device includes a gate stack structure and a plurality of channel structures. The gate stack structure includes an insulating interlayer and a gate conductive layer that are alternately stacked. The plurality of channel holes is formed in the gate stack structure. The plurality of channel holes includes a fluorine-containing layer, a first blocking layer, and a charge-trapping layer. The fluorine-containing layer is formed on surfaces of the channel holes for forming the plurality of channel structures. The first blocking layer is formed on the fluorine-containing layer along the surfaces of the channel holes. The charge-trapping layer is formed on the first blocking layer along the surfaces of the channel holes.

Abstract: A semiconductor device includes: a stack structure including gate patterns and insulating patterns; a channel layer penetrating the stack structure; a memory layer penetrating the stack structure, the memory layer surrounding the channel layer; and a select transistor connected to the channel layer. The select transistor includes: a carbon layer Schottky-joined with the channel layer; a select gate spaced apart from the carbon layer; and a gate insulating layer between the select gate and the carbon layer.

Abstract: A connector structure includes an insulating case, a terminal set and a grounding component. The terminal set is configured in the insulating case. The terminal set further includes a first terminal set, and the first terminal set includes a plurality of signal terminals and a plurality of grounding terminals. The grounding component is configured in the insulating case. The grounding component includes a component body and a graphene layer configured on a surface of the component body. The first grounding terminals are connected in series by contacting the graphene layer.

Abstract: A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.

Abstract: A metal-oxide semiconductor module includes multiple metal-oxide semiconductor components separated from one another by at least one first trench. Each of the metal-oxide semiconductor components includes a heavily doped semiconductor layer which includes a drain region, an epitaxial layer which is formed with an indentation such that the drain region is partially exposed from the epitaxial layer, and a metallic patterned contact unit. The epitaxial layer also includes a source region and a gate region that are spaced-apart formed therein. The metallic patterned contact unit includes source, gate, and drain patterned contacts which are electrically connected to the source, gate, and drain regions, respectively. A light-emitting diode display device including the metal-oxide semiconductor module is also disclosed.

Abstract: A memory controller that controls a memory device including a memory block includes an initial program controller configured to control the memory device to program at least one or more monitoring memory cells from among memory cells respectively connected to monitoring word lines from among a plurality of word lines connected to the memory block, a pre-read controller configured to generate a shifting information of a threshold voltage distribution of the monitoring memory cells based on a result of reading the monitoring memory cells before a read operation is performed on the memory block, and a pre-program controller configured to control the memory device to perform the read operation after applying a pre-program voltage having a voltage level determined according to the shifting information to the plurality of word lines.

Abstract: A precision agriculture implementation method by UAV systems and artificial intelligence image processing technologies provides an unmanned aerial vehicle (UAV), a wireless communication device, a central control unit, and a spray device and a multispectral camera installed to the UAV. The farming area is divided into an array of blocks. The central control unit controls the UAV to fly over the blocks according to navigation parameters and the multispectral camera to capture a multispectral image of each block. A projected leaf area index (PLAI) and a normalized difference vegetation index (NDVI) of each block are calculated by the multispectral image, and a spray control mode of the spray device of the corresponding block is set according to the PLAI and NDVI. The spray device is controlled to spray a water solution, salt solution, fertilizer solution, and/or pesticide solution to the corresponding block according to the spray control mode.

Abstract: Capacitance networks for enhancing high voltage operation of high electron mobility transistors (HEMTs) are presented herein. A capacitance network, integrated and/or external, may be provided with a fixed number of capacitively coupled field plates to distribute the electric field in the drift region. The capacitively coupled field plates may advantageously be fabricated on the same metal layer to lower cost; and the capacitance network may be provided to control field plate potentials. The potentials on each field plate may be pre-determined through the capacitance network, resulting in a uniform, and/or a substantially uniform electric field distribution along the drift region.

Abstract: A semiconductor device includes: a stack structure including gate patterns and insulating patterns; a channel layer penetrating the stack structure; a memory layer penetrating the stack structure, the memory layer surrounding the channel layer; and a select transistor connected to the channel layer. The select transistor includes: a carbon layer Schottky-joined with the channel layer; a select gate spaced apart from the carbon layer; and a gate insulating layer between the select gate and the carbon layer.

Abstract: Coupled polysilicon guard rings for enhancing breakdown voltage in a power semiconductor device are presented herein. Polysilicon guard rings are disposed above the power device drift region and electrically coupled to power device regions (e.g., device diffusions) so as to spread electric fields associated with an operating voltage. Additionally, PN junctions (i.e., p-type and n-type junctions) are formed within the polysilicon guard rings to operate in reverse bias with a low leakage current between the power device regions (e.g., device diffusions). Low leakage current may advantageously enhance the electric field spreading without deleteriously affecting existing (i.e., normal) power device performance; and enhanced electric field spreading may in turn reduce breakdown-voltage drift.

Abstract: An electrical connection module and a power supply integration structure of a connection interface of the electrical connection module are disclosed. The electrical connection module includes a connection body and a terminal structure. The connection body has a jack communicating with the inside of the connection body for installing the terminal structure in the connection body to communicate with the jack. The terminal structure includes multiple terminals arranged in two rows. Each row has one or more power terminals. The power terminal in one row is defined as a positive pin, the power terminal of the other row is defined as a negative pin. An end of the power terminal in each row is electrically connected to a conductive part respectively. The electrical connection module is disposed across a power guide base, and the conductive part is in contact with the power guide base to for the power integration.