Patents by Inventor Chang-Yong Ahn
Chang-Yong Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11912910Abstract: A conductive film laminate according to an embodiment of the present disclosure includes a carrier substrate, a conductive film liner on the carrier substrate, and a conductive adhesive film formed on the conductive film liner. The conductive film liner and the conductive adhesive film may form a cut pattern which does not cover the entire carrier substrate. The conductive adhesive film having a narrow width can be stably supplied on the carrier substrate. The conductive adhesive film may be used as an anisotropic conductive film for a bonding process of a touch sensor.Type: GrantFiled: March 25, 2021Date of Patent: February 27, 2024Assignee: DONGWOO FINE-CHEM CO., LTD.Inventors: Hyuk Hwan Kwon, Sun Kwon Ahn, Chang Yong Lee
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Patent number: 11747988Abstract: A semiconductor memory apparatus includes a memory bank circuit and a bandwidth control circuit. The memory bank circuit stores normal data, an error correction code, and a meta information code. The bandwidth control circuit controls bandwidths of the error correction code and the meta information code based on bandwidth option information.Type: GrantFiled: November 29, 2021Date of Patent: September 5, 2023Assignee: SK hynix Inc.Inventors: Chang Yong Ahn, Sung Hak Lee
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Publication number: 20230032148Abstract: A semiconductor memory apparatus includes a memory bank circuit and a bandwidth control circuit. The memory bank circuit stores normal data, an error correction code, and a meta information code. The bandwidth control circuit controls bandwidths of the error correction code and the meta information code based on bandwidth option information.Type: ApplicationFiled: November 29, 2021Publication date: February 2, 2023Applicant: SK hynix Inc.Inventors: Chang Yong AHN, Sung Hak LEE
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Patent number: 11037623Abstract: A semiconductor memory device includes a memory cell array, a storage circuit suitable for storing pattern data, a data input circuit suitable for receiving normal write data from an external device, a comparison circuit suitable for comparing the pattern data with the normal write data based on a pre-read control signal, and generating a comparison signal corresponding to the comparison result, and a write circuit suitable for writing the pattern data to the memory cell array based on a pre-write control signal, and writing some of the normal write data to the memory cell array based on a normal write control signal and the comparison signal.Type: GrantFiled: October 9, 2019Date of Patent: June 15, 2021Assignee: SK hynix Inc.Inventors: Chang-Yong Ahn, Han-Suk Ko
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Publication number: 20200234764Abstract: A semiconductor memory device includes a memory cell array, a storage circuit suitable for storing pattern data, a data input circuit suitable for receiving normal write data from an external device, a comparison circuit suitable for comparing the pattern data with the normal write data based on a pre-read control signal, and generating a comparison signal corresponding to the comparison result, and a write circuit suitable for writing the pattern data to the memory cell array based on a pre-write control signal, and writing some of the normal write data to the memory cell array based on a normal write control signal and the comparison signal.Type: ApplicationFiled: October 9, 2019Publication date: July 23, 2020Inventors: Chang-Yong AHN, Han-Suk KO
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Publication number: 20180261263Abstract: A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.Type: ApplicationFiled: May 15, 2018Publication date: September 13, 2018Inventors: Chang Yong AHN, Jun Ho CHEON
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Patent number: 9997211Abstract: A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.Type: GrantFiled: December 14, 2016Date of Patent: June 12, 2018Assignee: SK Hynix Inc.Inventors: Chang Yong Ahn, Jun Ho Cheon
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Patent number: 9893143Abstract: An analog capacitor is disclosed. The analog capacitor may include a main analog capacitor, an interlayer insulating layer, and a plurality of stacked sub analog capacitors. The main analog capacitor may be formed over a semiconductor substrate. The interlayer insulating layer may be interposed between the semiconductor substrate and the main analog capacitor. The plurality of stacked sub analog capacitors may be inserted into the interlayer insulating layer.Type: GrantFiled: September 15, 2016Date of Patent: February 13, 2018Assignee: SK hynix Inc.Inventors: Jun Ho Cheon, Chang Yong Ahn, Seok Joon Kang
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Publication number: 20170372792Abstract: A memory test system may include a memory apparatus and a test apparatus. The test apparatus may be configured to generate a code distribution of noble cells. The test apparatus may be configured to generate a mass data code distribution and a test result based on the code distribution of noble cells.Type: ApplicationFiled: March 30, 2017Publication date: December 28, 2017Applicant: SK hynix Inc.Inventors: Hak Song KIM, Chang Yong AHN
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Publication number: 20170358351Abstract: A memory apparatus includes a write driver, a sense amplifier and a reference voltage setting circuit. The write driver programs a set data or a reset data into a memory cell. The sense amplifier generates an output signal by sensing data stored in the memory cell. The reference voltage setting circuit sets a set reference voltage having a lowest level to satisfy a set data distribution, and sets a set-up reset reference voltage from the set reference voltage.Type: ApplicationFiled: February 27, 2017Publication date: December 14, 2017Applicant: SK hynix Inc.Inventor: Chang Yong AHN
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Patent number: 9842648Abstract: A memory apparatus includes a write driver, a sense amplifier and a reference voltage setting circuit. The write driver programs a set data or a reset data into a memory cell. The sense amplifier generates an output signal by sensing data stored in the memory cell. The reference voltage setting circuit sets a set reference voltage having a lowest level to satisfy a set data distribution, and sets a set-up reset reference voltage from the set reference voltage.Type: GrantFiled: February 27, 2017Date of Patent: December 12, 2017Assignee: SK hynix Inc.Inventor: Chang Yong Ahn
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Publication number: 20170337950Abstract: A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.Type: ApplicationFiled: December 14, 2016Publication date: November 23, 2017Inventors: Chang Yong AHN, Jun Ho CHEON
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Publication number: 20170288012Abstract: An analog capacitor is disclosed. The analog capacitor may include a main analog capacitor, an interlayer insulating layer, and a plurality of stacked sub analog capacitors. The main analog capacitor may be formed over a semiconductor substrate. The interlayer insulating layer may be interposed between the semiconductor substrate and the main analog capacitor. The plurality of stacked sub analog capacitors may be inserted into the interlayer insulating layer.Type: ApplicationFiled: September 15, 2016Publication date: October 5, 2017Inventors: Jun Ho CHEON, Chang Yong AHN, Seok Joon KANG
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Patent number: 9734904Abstract: A digital LDO regulator includes a first comparison circuit to compare an output voltage with a reference voltage and to output a reference load switching signal when the output voltage rises above the reference voltage, a logic circuit to output a control current in response to the reference load switching signal, a second comparison circuit to compare the output voltage with a transient reference voltage and to output a transient load switching signal when the output voltage rises above the transient reference voltage, a switching circuit to control the logic circuit to pass a transient current in response to the transient load switching signal, a circuit to provide a mirroring current to the logic circuit after a transient state, a load current supply circuit to switch in response to the control current and to supply a load current, and a capacitor coupled to the load current supply circuit.Type: GrantFiled: February 2, 2017Date of Patent: August 15, 2017Assignees: SK HYNIX INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Gyu Hyeong Cho, Sung Won Choi, Chang Yong Ahn
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Patent number: 9666247Abstract: A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal as soon as the comparison flag signal is enabled.Type: GrantFiled: May 17, 2016Date of Patent: May 30, 2017Assignee: SK hynix Inc.Inventors: Chang Yong Ahn, Ho Seok Em
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Patent number: 9648660Abstract: The disclosure is related tracking area management in a femtocell network. A mobility management entity may receive, from a femtocell base station, macrocell tracking area information associated with the femtocell base station. The mobility management entity may combine the received macrocell tracking area information with femtocell tracking area information associated with the femtocell base station and storing the combined tracking area information as integrated tracking area information.Type: GrantFiled: June 17, 2013Date of Patent: May 9, 2017Assignee: KT CORPORATIONInventors: Tae-Won Ban, Young-Han Kim, Chang-Yong Ahn, Hyun-Beom Lee, Byoung-Jin Choi
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Patent number: 9508411Abstract: A word line driver circuit according to an embodiment includes a driving unit configured to output a sub word line driving signal in response to a word line select signal and a main word line driving signal, a transmission unit configured to transmit the sub word line driving signal to a word line in response to a first enable signal, and a precharge unit configured to precharge a potential of the word line.Type: GrantFiled: September 15, 2014Date of Patent: November 29, 2016Assignee: SK HYNIX INC.Inventors: Chang Yong Ahn, Yoon Jae Shin
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Publication number: 20160260464Abstract: A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal as soon as the comparison flag signal is enabled.Type: ApplicationFiled: May 17, 2016Publication date: September 8, 2016Inventors: Chang Yong AHN, Ho Seok EM
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Patent number: 9379725Abstract: A digital to analog converter may include a reference voltage generation unit that generates a reference voltage and a plurality of unit conversion units connected through an output node. The plurality of unit conversion units may set a voltage level of the output node in response to digital codes and the reference voltage.Type: GrantFiled: January 19, 2015Date of Patent: June 28, 2016Assignee: SK hynix Inc.Inventors: Chang Yong Ahn, Jun Ho Cheon
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Patent number: 9368171Abstract: A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal in response to a write command, and generate the write signal for a following write operation as soon as the comparison flag signal is at a predetermined level.Type: GrantFiled: December 8, 2014Date of Patent: June 14, 2016Assignee: SK HYNIX INCInventors: Chang Yong Ahn, Ho Seok Em