Abstract: A write driver is configured to determine a magnitude and an application time of a pre-emphasis current pulse in response to control codes generated according to parasitic components on a path from a write driver to a program target cell and a resistance value of the program target cell, and supply a preset program current to a memory circuit block by adding a pre-emphasis current to the preset program current in a program mode.

Abstract: A digital to analog converter includes a reference voltage generation unit that generates a reference voltage, and a plurality of unit conversion units. A number of unit conversion units to be activated are decided in response to digital codes. An activated unit conversion unit drives a control node to a voltage level corresponding to a voltage level of the reference voltage, and a deactivated unit conversion unit substantially maintains the control node to a voltage level greater than a voltage level of a ground voltage.

Abstract: A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal in response to a write command, and generate the write signal for a following write operation as soon as the comparison flag signal is at a predetermined level.

Abstract: A write driver is configured to determine a magnitude and an application time of a pre-emphasis current pulse in response to control codes generated according to parasitic components on a path from a write driver to a program target cell and a resistance value of the program target cell, and supply a preset program current to a memory circuit block by adding a pre-emphasis current to the preset program current in a program mode.

Abstract: Provided are apparatus and method for controlling handover to prevent femtocell interference. The apparatus may include an event receiving module, a handover determining module, and an inter-frequency processing module. The event receiving module may be configured to receive a control message from user equipment. The handover determining module may be configured to analyze the received control message and determine whether the control message includes a request of inter-cell handover from a first cell base station of the first cell to a second cell base station of one of the second cells. The inter-frequency processing module may be configured to perform inter-frequency handover using an unshared frequency when the handover determining module determines that the control message includes the request of inter-cell handover.

Abstract: A world line driver circuit according to an embodiment includes a driving unit configured to output a sub word line driving signal in response to a word line select signal and a main word line driving signal, a transmission unit configured to transmit the sub word line driving signal to a word line in response to a first enable signal, and a precharge unit configured to precharge a potential of the word line.

Abstract: A semiconductor memory apparatus may include a read/write circuit unit configured to receive an external voltage, to read data from a memory cell array, and to generate a pre-read signal, while an internal voltage is generated during a test mode, and a controller configured to selectively drive a write circuit unit in response to the pre-read signal.

Abstract: Described embodiments provide for handover in a long term evolution (LTE) communication network. A LTE macrocell base station may receive a measurement report from user equipment while providing a communication service to the user equipment located within a service area of the LTE macrocell base station, and determine whether or not the neighbor cell is a LTE macrocell or a LTE femtocell based on the measurement report. The LTE macrocell base station may initiate hand-over of the user equipment to a neighbor WCDMA macrocell base station when the neighbor cell is determined as the LTE femtocell.

Abstract: A method for driving a nonvolatile memory apparatus includes: a data storage preparation step of setting a write control voltage to a first level of voltage; a data storage step of driving a driving transistor through the write control voltage to generate a write current, and storing an external data in a memory cell through the write current; a data detection step of varying the write control voltage by a predetermined level from a preset voltage level, and reading the data stored in the memory cell; and a data verification step of determining whether the stored data coincides with the external data or not, and repeating the data storage step and the data detection step according to a result of the determining.

Abstract: A method for measuring a write current of a semiconductor memory device includes the steps of: programming initial data into memory cells which are to be programmed substantially at the same time; determining whether the memory cells are programmed into the same state or not; inputting test data when the memory cells are programmed into the same state; setting write current paths of the memory cells by comparing the initial data and the test data; and measuring a write current consumed when the test data are programmed into the memory cells.

Abstract: Provided are apparatus and method for controlling handover to prevent femtocell interference. The apparatus may include an event receiving module, a handover determining module, and an inter-frequency processing module. The event receiving module may be configured to receive a control message from user equipment. The handover determining module may be configured to analyze the received control message and determine whether the control message includes a request of inter-cell handover from a first cell base station of the first cell to a second cell base station of one of the second cells. The inter-frequency processing module may be configured to perform inter-frequency handover using an unshared frequency when the handover determining module determines that the control message includes the request of inter-cell handover.

Abstract: A nonvolatile memory apparatus includes a memory cell configured to receive a first current and a second current through a bit line which is connected to a sensing node; a sensing node level control unit configured to be driven in response to a control signal, compare a reference voltage and a voltage of the sensing node, and output a driving signal to a driving node; a first current driving unit configured to output the first current to the driving node by using a first driving voltage in response to the driving signal; and a current control unit configured to perform a discharge operation of the bit line or electrically connect the driving node and the sensing node, in response to the control signal.

Abstract: A variable resistance memory device includes memory cells arranged at a region where word lines and bit lines cross each other, control logic configured to generate a command flag indicative of a program operation mode in response to a program command provided from an external device and configured to control the program operation of the memory cells based on the command flag and a write driver configured to be activated in response to the flag command and configured to supply a program current to the memory cells.

Abstract: A program pulse generation circuit includes: a set pulse generator configured to apply a set pulse to an output node in response to a driving signal, a set pulse control signal, and a first switching signal, and a current controller configured to control step reductions forming the set pulse in response to the driving signal and a second switching signal.

Abstract: Provided are apparatus and method for setting a cyclic prefix length according to a type of a base station. The apparatus may include a memory, a receiver, a selector, and an inserter. The receiver may be configured to store and to manage a plurality of prefix lengths associated with base station types. The receiver may be configured to receive base station information from a base station. The selector may be configured to select a prefix length from the plurality of prefix length based on the received base station information. The inserter may be configured to insert a cyclic prefix having the determined prefix length in a guard interval of a transmission frame.

Abstract: A nonvolatile memory apparatus includes a memory cell configured to receive a first current and a second current through a bit line which is connected to a sensing node; a sensing node level control unit configured to be driven in response to a control signal, compare a reference voltage and a voltage of the sensing node, and output a driving signal to a driving node; a first current driving unit configured to output the first current to the driving node by using a first driving voltage in response to the driving signal; and a current control unit configured to perform a discharge operation of the bit line or electrically connect the driving node and the sensing node, in response to the control signal.

Abstract: A method for measuring a write current of a semiconductor memory device includes the steps of: programming initial data into memory cells which are to be programmed substantially at the same time; determining whether the memory cells are programmed into the same state or not; inputting test data when the memory cells are programmed into the same state; setting write current paths of the memory cells by comparing the initial data and the test data; and measuring a write current consumed when the test data are programmed into the memory cells.

Abstract: A method for driving a nonvolatile memory apparatus includes: a data storage preparation step of setting a write control voltage to a first level of voltage; a data storage step of driving a driving transistor through the write control voltage to generate a write current, and storing an external data in a memory cell through the write current; a data detection step of varying the write control voltage by a predetermined level from a preset voltage level, and reading the data stored in the memory cell; and a data verification step of determining whether the stored data coincides with the external data or not, and repeating the data storage step and the data detection step according to a result of the determining.

Abstract: The disclosure is related tracking area management in a femtocell network. A mobility management entity may receive, from a femtocell base station, macrocell tracking area information associated with the femtocell base station. The mobility management entity may combine the received macrocell tracking area information with femtocell tracking area information associated with the femtocell base station and storing the combined tracking area information as integrated tracking area information.

Abstract: A variable resistance memory device includes memory cells arranged at a region where word lines and bit lines cross each other, control logic configured to generate a command flag indicative of a program operation mode in response to a program command provided from an external device and configured to control the program operation of the memory cells based on the command flag and a write driver configured to be activated in response to the flag command and configured to supply a program current to the memory cells.