Patents by Inventor Changming Jin

Changming Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935213
    Abstract: A laparoscopic image smoke removal method based on a generative adversarial network, and belongs to the technical field of computer vision. The method includes: processing a laparoscopic image sample to be processed using a smoke mask segmentation network to acquire a smoke mask image; inputting the laparoscopic image sample to be processed and the smoke mask image into a smoke removal network, and extracting features of the laparoscopic image sample to be processed using a multi-level smoke feature extractor to acquire a light smoke feature vector and a heavy smoke feature vector; and acquiring, according to the light smoke feature vector, the heavy smoke feature vector and the smoke mask image, a smoke-free laparoscopic image by filtering out smoke information and maintaining a laparoscopic image by using a mask shielding effect. The method has the technical effects of robustness and ability of being embedded into a laparoscopic device for use.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: March 19, 2024
    Assignee: Shandong Normal University
    Inventors: Dengwang Li, Pu Huang, Tingxuan Hong, Jie Xue, Hua Lu, Xueyao Liu, Baolong Tian, Changming Gu, Bin Jin, Xiangyu Zhai
  • Patent number: 11913395
    Abstract: An intelligent control method for engine initiation, including: determining whether a current driving mode satisfies a predetermined driving mode; when the current driving mode satisfies the predetermined driving mode, acquiring a current remaining capacity of a battery; determining whether the current remaining capacity is greater than a predetermined capacity threshold value; when the current remaining capacity is greater than the predetermined capacity threshold value, not starting an engine, otherwise, acquiring a catalyst temperature and a vehicle operating state; determining, according to the vehicle operating state, whether the catalyst temperature is less than a predetermined temperature threshold value; when the catalyst temperature is not less than the predetermined temperature threshold value, driving the engine to rotate clockwise to start same in a fuel cut-off manner, otherwise, heating a catalyst by a heating plate until the catalyst temperature is not less than the predetermined temperature th
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 27, 2024
    Assignees: ZHEJIANG GEELY HOLDING GROUP CO., LTD., NINGBO GEELY ROYAL ENGINE COMPONENTS CO., LTD., Aurobay Technology Co., Ltd.
    Inventors: Conghui An, Yiqiang Liu, Zhiwei Qiao, Changming Jin, Zhengxing Dai, Jiang Tang, Junjie Guo
  • Publication number: 20230407803
    Abstract: An intelligent control method for engine initiation, including: determining whether a current driving mode satisfies a predetermined driving mode; when the current driving mode satisfies the predetermined driving mode, acquiring a current remaining capacity of a battery; determining whether the current remaining capacity is greater than a predetermined capacity threshold value; when the current remaining capacity is greater than the predetermined capacity threshold value, not starting an engine, otherwise, acquiring a catalyst temperature and a vehicle operating state; determining, according to the vehicle operating state, whether the catalyst temperature is less than a predetermined temperature threshold value; when the catalyst temperature is not less than the predetermined temperature threshold value, driving the engine to rotate clockwise to start same in a fuel cut-off manner, otherwise, heating a catalyst by a heating plate until the catalyst temperature is not less than the predetermined temperature th
    Type: Application
    Filed: November 19, 2021
    Publication date: December 21, 2023
    Inventors: Conghui AN, Yiqiang LIU, Zhiwei QIAO, Changming JIN, Zhengxing DAI, Jiang TANG, Junjie GUO
  • Publication number: 20220102567
    Abstract: According to the embodiments provided herein, back contacts for photovoltaic devices can include one or more metal oxynitride layers.
    Type: Application
    Filed: February 6, 2020
    Publication date: March 31, 2022
    Applicant: First Solar, Inc.
    Inventors: Changming Jin, Vijay Karthik Sankar
  • Patent number: 10896991
    Abstract: Disclosed are methods for the surface cleaning and passivation of PV absorbers, such as CdTe substrates usable in solar cells, and devices made by such methods. In some embodiments, the method involves an anode layer ion source (ALIS) plasma discharge process to clean and oxidize a CdTe surface to produce a thin oxide layer between the CdTe layer and subsequent back contact layer(s).
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 19, 2021
    Assignee: First Solar, Inc.
    Inventors: Changming Jin, Sanghyun Lee, Jun-Ying Zhang
  • Publication number: 20190348561
    Abstract: Disclosed are methods for the surface cleaning and passivation of PV absorbers, such as CdTe substrates usable in solar cells, and devices made by such methods. In some embodiments, the method involves an anode layer ion source (ALIS) plasma discharge process to clean and oxidize a CdTe surface to produce a thin oxide layer between the CdTe layer and subsequent back contact layer(s).
    Type: Application
    Filed: July 26, 2019
    Publication date: November 14, 2019
    Applicant: First Solar, Inc.
    Inventors: Changming Jin, Sanghyun Lee, Jun-Ying Zhang
  • Patent number: 10367110
    Abstract: Disclosed are methods for the surface cleaning and passivation of PV absorbers, such as CdTe substrates usable in solar cells, and devices made by such methods. In some embodiments, the method involves an anode layer ion source (ALIS) plasma discharge process to clean and oxidize a CdTe surface to produce a thin oxide layer between the CdTe layer and subsequent back contact layer(s).
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: July 30, 2019
    Assignee: First Solar, Inc.
    Inventors: Changming Jin, Sanghyun Lee, Jun-Ying Zhang
  • Publication number: 20180323332
    Abstract: A vapor transport deposition system and method that includes a vaporizer and distributor unit and at least one auxiliary process unit for integrating thin-film layer deposition with one or more pre- or post-deposition processes.
    Type: Application
    Filed: July 19, 2018
    Publication date: November 8, 2018
    Applicant: First Solar, Inc.
    Inventors: John Barden, Changming Jin, Feng Liao, Rick C. Powell, Gang Xiong
  • Publication number: 20170170353
    Abstract: Disclosed are methods for the surface cleaning and passivation of PV absorbers, such as CdTe substrates usable in solar cells, and devices made by such methods. In some embodiments, the method involves an anode layer ion source (ALIS) plasma discharge process to clean and oxidize a CdTe surface to produce a thin oxide layer between the CdTe layer and subsequent back contact layer(s).
    Type: Application
    Filed: December 8, 2016
    Publication date: June 15, 2017
    Applicant: First Solar, Inc.
    Inventors: Changming Jin, Sanghyun Lee, Jun-Ying Zhang
  • Patent number: 7910936
    Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: March 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Kumar Ajmera, Patricia Beauregard Smith, Changming Jin
  • Patent number: 7745335
    Abstract: A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Ju-Ai Ruan, Changming Jin, Sopa Chevacharoenkul, Satyavolu Papa Rao, Tae Seung Kim
  • Patent number: 7732324
    Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: June 8, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Ju-Ai Ruan, Sameer K. Ajmera, Changming Jin, Anand J. Reddy, Tae S. Kim
  • Publication number: 20090160059
    Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Ju-Ai Ruan, Sameer K. Ajmera, Changming Jin, Anand J. Reddy, Tae S. Kim
  • Publication number: 20090115030
    Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.
    Type: Application
    Filed: December 9, 2008
    Publication date: May 7, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Sameer Kumar Ajmera, Patricia Beauregard Smith, Changming Jin
  • Patent number: 7476602
    Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: January 13, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Kumar Ajmera, Patricia Beauregard Smith, Changming Jin
  • Publication number: 20080150131
    Abstract: A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 26, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Ju-Ai Ruan, Changming Jin, Sopa Chevacharoenkul, Satyavolu Papa Rao, Tae Seung Kim
  • Patent number: 7187080
    Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: March 6, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Qing-Tang Jiang, Changming Jin, Joseph D. Luttmer
  • Publication number: 20060172552
    Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 3, 2006
    Inventors: Sameer Ajmera, Patricia Smith, Changming Jin
  • Patent number: 7037823
    Abstract: A trench and via structure is formed in a low k dielectric layer (100) formed over a silicon substrate (10). Super critical CO2 and a first silylization agent are used to form a chemically bonded high density surface layer (160). Silanol species are removed from the low k dielectric layer (100) using super critical CO2 and a second silylization agent. A barrier layer (190) and copper (200) are used to fill the trench and via structure.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: May 2, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Phillip D. Matz, Sameer Ajmera, Changming Jin, Trace Q. Hurd
  • Publication number: 20050233586
    Abstract: A trench and via structure is formed in a low k dielectric layer (100) formed over a silicon substrate (10). Super critical CO2 and a first silylization agent are used to form a chemically bonded high density surface layer (160). Silanol species are removed from the low k dielectric layer (100) using super critical CO2 and a second silylization agent. A barrier layer (190) and copper (200) are used to fill the trench and via structure.
    Type: Application
    Filed: July 27, 2004
    Publication date: October 20, 2005
    Inventors: Phillip Matz, Sameer Ajmera, Changming Jin, Trace Hurd